发明授权
- 专利标题： Logic module core cell for gate arrays
- 专利标题（中）： 门阵列的逻辑模块核心单元
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申请号： US318322申请日： 1994-10-05
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公开(公告)号： US5491431A公开(公告)日： 1996-02-13
- 发明人: Mitra Nasserbakht
- 申请人： Mitra Nasserbakht
- 申请人地址： TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： TX Dallas
- 主分类号： H03K19/173
- IPC分类号： H03K19/173
摘要：
A logic module for use in gate arrays and the like includes five two input multiplexers 50, 52, 54, 56, 58. The module includes 10 data input terminals I1, I2, I3, I4, I5, I6, I7, I8, I9, I10. The first input terminals I1, I2 are connected to the data input terminals of multiplexer 50. Inputs I3, I4 and I5 are connected respectively to the select, the first data and second data inputs to multiplexer 52. Inputs I6, I7 are connected to the data inputs of multiplexer 54. Inputs I8, I9, I10 are connected to the first data, second data and select inputs to multiplexer 56. The output of multiplexer 52 is connected to the select input to multiplexers 50 and 54. The output of multiplexer 56 is connected to the select input to multiplexer 58 while the outputs of multiplexers 50 and 54 are respectively connected to the first and second data input to multiplexer 58. The output of multiplexer 58 comprises the logic circuit output O.