发明授权
- 专利标题： Transistor layout for semiconductor integrated circuit
- 专利标题（中）： 半导体集成电路晶体管布局
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申请号： US270085申请日： 1994-07-01
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公开(公告)号： US5498897A公开(公告)日： 1996-03-12
- 发明人: Katsuo Komatsuzaki , Masayasu Kawamura , Hidetoshi Iwai
- 申请人： Katsuo Komatsuzaki , Masayasu Kawamura , Hidetoshi Iwai
- 申请人地址： TX Dallas
- 专利权人： Texas Instruments Incorporated,Hitachi Ltd.
- 当前专利权人： Texas Instruments Incorporated,Hitachi Ltd.
- 当前专利权人地址： TX Dallas
- 主分类号： H01L27/105
- IPC分类号： H01L27/105 ; H01L27/11 ; H01L29/772
摘要：
A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that its channel length is small or channel width is large, and an input signal is applied from at least both end sides of the gate electrode thereof. Since the metal wiring layer for the input signal is formed on the gate electrode of the MOSFET, high-speed operation is possible without increasing the layout area. FIG. 1.