发明授权
- 专利标题: Residue circuit
- 专利标题(中): 残留电路
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申请号: US253057申请日: 1994-06-02
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公开(公告)号: US5499202A公开(公告)日: 1996-03-12
- 发明人: Tsugio Takahashi , Hitoshi Fujita , Hiroshi Okamoto
- 申请人: Tsugio Takahashi , Hitoshi Fujita , Hiroshi Okamoto
- 申请人地址: JPX Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX5-156294 19930602
- 主分类号: G06F7/496
- IPC分类号: G06F7/496 ; G06F7/72 ; G06F7/52 ; G06F7/50
摘要:
A residue circuit takes weights of even number bits of a dividend as 1 and weights of odd number bits of the dividend as 2. The circuit includes a plurality of adders for summing bits having weight 1 to output weight 1 at a summing output and weight 2 at a carry output, and a plurality of adders for summing bits having weight 2 to output weight 2 at a summing output and weight 1 at a carry output. With these adders, summing of respective bits of the dividend bits are performed taking the weights into account to repeat summing until the number of bits finally becomes 3 bits. Depending upon the pattern of this 3 bits, a remainder is output by a modulus 3 generation circuit.