Memory cell transistors are provided in which column structures (12a, 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the column structures (12a, 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36) are implanted in the semiconductor substrate. Drain regions (38) are also implanted in the column structures (12a, 14a).