发明授权
US5521880A Integrated circuit memory having control circuitry for shared data bus 失效
具有共享数据总线控制电路的集成电路存储器

Integrated circuit memory having control circuitry for shared data bus
摘要:
A memory system includes two memory arrays coupled to a global data bus via respective address decode circuits. Address control circuitry defaults to the weaker memory array upon receiving a new address such that the stronger memory array will not produce false values on the bus prior to stabilization of the address and proper decode. Consequently, the weaker memory array is not faced with a situation where it must overcome the previous false signal prior to developing the proper output values on the bus.
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