In partial scan testing of integrated circuits, for an arbitrary graph of an integrated circuit, a Boolean function is derived whose satisfying assignments directly correspond to feedback vertex sets of the graph. The Boolean function is then used for determining the minimum cost feedback vertex set. Boolean function representation using Binary Decision Diagrams (BDI)) in logic synthesis is used to solve the problem of representing the Boolean function efficiently, even for large graphs. The determined minimum cost feedback vertex set is used to select those memory elements in the integrated circuit comprising the scan chain.