公开(公告)号：US5522063A

公开(公告)日：1996-05-28

申请号：US127681

申请日：1993-09-27

申请人： Pranav N. Ashar ,  Sharad Malik

发明人： Pranav N. Ashar ,  Sharad Malik

IPC分类号： G01R31/3183 ,  G01R31/3185 ,  G06F15/00

CPC分类号： G01R31/318371 ,  G01R31/318586

摘要： In partial scan testing of integrated circuits, for an arbitrary graph of an integrated circuit, a Boolean function is derived whose satisfying assignments directly correspond to feedback vertex sets of the graph. The Boolean function is then used for determining the minimum cost feedback vertex set. Boolean function representation using Binary Decision Diagrams (BDI)) in logic synthesis is used to solve the problem of representing the Boolean function efficiently, even for large graphs. The determined minimum cost feedback vertex set is used to select those memory elements in the integrated circuit comprising the scan chain.

摘要翻译： 在集成电路的部分扫描测试中，对于集成电路的任意图形，导出其满意分配直接对应于图的反馈顶点集的布尔函数。 然后使用布尔函数来确定最小成本反馈顶点集。 逻辑综合中使用二进制决策图（BDI）的布尔函数表示法用于解决即使对于大图形也能有效地表示布尔函数的问题。 确定的最小成本反馈顶点组用于选择包括扫描链的集成电路中的那些存储器元件。

公开(公告)号：US5937183A

公开(公告)日：1999-08-10

申请号：US743804

申请日：1996-11-05

申请人： Pranav N. Ashar ,  Sharad Malik

发明人： Pranav N. Ashar ,  Sharad Malik

IPC分类号： G06F9/45 ,  G06F17/50 ,  G06F9/455

CPC分类号： G06F8/447 ,  G06F17/504

摘要： In compiled code simulation, a circuit to be simulated is converted or compiled into an executable so that running the executable produces the same output response as the circuit itself. In a binary decision diagram (BDD)-based compiled code simulator, the simulation executable for the circuit is derived from a BDD-based characteristic function representation of the circuit rather than by the heretofore used translation of Boolean operations in the original circuit into machine instructions.

摘要翻译： 在编译代码模拟中，要仿真的电路被转换或编译成可执行文件，以便运行可执行文件产生与电路本身相同的输出响应。 在基于二进制决策图（BDD）的编译代码模拟器中，电路的仿真可执行程序是从电路的基于BDD的特征函数表示得出的，而不是由原来的电路中的布尔运算转换成机器指令 。

公开(公告)号：US06816827B1

公开(公告)日：2004-11-09

申请号：US09410087

申请日：1999-10-01

申请人： Yang Xia ,  Pranav N. Ashar

发明人： Yang Xia ,  Pranav N. Ashar

IPC分类号： G06F1750

CPC分类号： G06F17/504

摘要： A design verification method for verifying hardware designs utilizing combinational loop logic. A design verification system is provided wherein a model checker receives both a mathematical representation of the functionality of a design and a set of properties against which the mathematical model is to be checked. If the design contains a combinational loop wherein the output directly depends on its own output and must be logically completed within a single bus cycle, then modifications to the model are undertaken. A minimal number of flip-flops are first added to the combinational loop in order to break up the combinational dependency. All of the states of a state machine model of the design are then supplemented with a twin state which is exactly the same as the original state. If the current state is an original state then the next cycle progresses the state machine to twin state of the particular original state. If the current state is a twin state, then the state machine progresses to the next new original state. Thus, by modifying the model in a generic straightforward manner, the design containing a combinational loop can be verified with currently available verification systems without requiring any modifications to the model checker itself.

公开(公告)号：US07346486B2

公开(公告)日：2008-03-18

申请号：US11040409

申请日：2005-01-21

申请人： Franjo Ivancic ,  Pranav N. Ashar ,  Malay Ganai ,  Aarti Gupta ,  Zijiang Yang

发明人： Franjo Ivancic ,  Pranav N. Ashar ,  Malay Ganai ,  Aarti Gupta ,  Zijiang Yang

IPC分类号： G06F9/45 ,  G06F7/60 ,  G06F9/44 ,  G06F11/00

CPC分类号： G06F17/504 ,  G06F11/3608

摘要： A system and method is disclosed for formal verification of software programs that advantageously translates the software, which can have bounded recursion, into a Boolean representation comprised of basic blocks and which applies SAT-based model checking to the Boolean representation.

摘要翻译： 公开了一种软件程序的形式验证的系统和方法，其有利地将可以具有有界递归的软件翻译成由基本块组成的布尔表示，并将基于SAT的模型检查应用于布尔表示。