Structure capable of simultaneously testing redundant and non-redundant memory elements during stress testing of an integrated circuit memory device

发明授权

US5530674A Structure capable of simultaneously testing redundant and non-redundant memory elements during stress testing of an integrated circuit memory device 失效

标题翻译：能够在集成电路存储器件的压力测试期间同时测试冗余和非冗余存储元件的结构

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专利标题： Structure capable of simultaneously testing redundant and non-redundant memory elements during stress testing of an integrated circuit memory device
专利标题（中）： 能够在集成电路存储器件的压力测试期间同时测试冗余和非冗余存储元件的结构
申请号： US235161

申请日： 1994-04-29
公开(公告)号： US5530674A

公开(公告)日： 1996-06-25
发明人: David C. McClure , Thomas A. Teel
申请人： David C. McClure , Thomas A. Teel
申请人地址： TX Carrollton
专利权人： SGS-Thomson Microelectronics, Inc.
当前专利权人： SGS-Thomson Microelectronics, Inc.
当前专利权人地址： TX Carrollton
主分类号： G11C29/00
IPC分类号： G11C29/00 ; G11C29/24 ; G11C29/50

Structure capable of simultaneously testing redundant and non-redundant
memory elements during stress testing of an integrated circuit memory
device

摘要：

The redundant elements of an integrated circuit memory device having a plurality of redundant and non-redundant elements such as rows, columns, wordlines, and blocks, may be selectively enabled during a stress test mode so that both redundant elements and non-redundant elements may be stress tested concurrently. Enabling capabilities contained within the redundant element circuitry selectively enables the redundant elements when a stress test signal is equal to a predetermined value, indicative of a stress test mode.

摘要（中）：

具有多个冗余和非冗余元件（诸如行，列，字线和块）的集成电路存储器件的冗余元件可以在压力测试模式期间被选择性地启用，使得冗余元件和非冗余元件可以同时进行压力测试。包含在冗余元件电路内的启用功能在压力测试信号等于预定值时，选择性地启用冗余元件，表示压力测试模式。

公开/授权文献

US4373112A Cable holder 公开/授权日：1983-02-08

信息查询

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IPC分类:

G	物理
G11	信息存储
G11C	静态存储器（半导体存储器件入H01L，如H01L27/108-H01L27/11597）
G11C29/00	存储器正确运行的校验；备用或离线操作期间测试存储器