发明授权
US5538913A Process for fabricating MOS transistors having full-overlap
lightly-doped drain structure
失效
制造具有全重叠轻掺杂漏极结构的MOS晶体管的工艺
- 专利标题: Process for fabricating MOS transistors having full-overlap lightly-doped drain structure
- 专利标题(中): 制造具有全重叠轻掺杂漏极结构的MOS晶体管的工艺
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申请号: US558958申请日: 1995-11-13
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公开(公告)号: US5538913A公开(公告)日: 1996-07-23
- 发明人: Gary Hong
- 申请人: Gary Hong
- 申请人地址: TWX Hsinchu
- 专利权人: United Microelectronics Corporation
- 当前专利权人: United Microelectronics Corporation
- 当前专利权人地址: TWX Hsinchu
- 主分类号: H01L21/28
- IPC分类号: H01L21/28 ; H01L21/336 ; H01L29/10 ; H01L29/78 ; H01L21/265
摘要:
A process for fabricating a MOS transistor having a full-overlap lightly-doped drain is disclosed. The MOS transistor is fabricated on a semiconductor silicon substrate that has formed thereon a field oxide layer that defines the active region of the MOS transistor. A field oxide layer is first used as the shielding mask for implanting impurities into the active region thereby forming a lightly-doped region. A shielding layer is then formed with an opening over the surface of the substrate. The opening has two sidewalls that generally define the channel region for the MOS transistor. A gate insulation layer is then formed over the surface of the substrate within the confinement of the opening. Conducting sidewall spacers are then formed over the sidewalls of the opening. The shielding layer and conducting sidewall spacers are then utilized as the shielding mask for implanting impurities into the lightly-doped region, thereby forming the channel region for the MOS transistor. A conducting layer is then formed over the surface of the gate insulation layer in the space as confined within the conducting sidewall spacers, wherein the conducting layer and the conducting sidewall spacers constitute the gate for the MOS transistor. The shielding layer is then removed. The gate and field oxide layer are used as the shielding mask for implanting impurities into the substrate, thereby forming a heavily-doped region, wherein the lightly-doped region completely overlaps the gate, and extends into the drain and source regions of the MOS transistor.
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