发明授权
- 专利标题： Isolation structure for semiconductor device
- 专利标题（中）： 半导体器件隔离结构
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申请号： US278289申请日： 1994-07-21
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公开(公告)号： US5541440A公开(公告)日： 1996-07-30
- 发明人: Yutaka Kozai , Kiyoto Watabe , Tatsuhiko Ikeda
- 申请人： Yutaka Kozai , Kiyoto Watabe , Tatsuhiko Ikeda
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX5-186446 19930728
- 主分类号： H01L21/76
- IPC分类号： H01L21/76 ; H01L21/763 ; H01L21/8249 ; H01L27/06 ; H01L29/06 ; H01L29/00
摘要：
It is an object of the present invention to provide a semiconductor device which has a high electrical isolation capability and an enhanced electrical reliability for avoiding short circuit of individual conductive layers, and the present invention also provides a method of manufacturing such a semiconductor device. An n.sup.+ buried layer and an n.sup.- epitaxial growth layer are formed on a p.sup.- silicon substrate. An element isolation oxide film having a through hole is formed on the surface of n.sup.- epitaxial growth layer. A trench which penetrates through n.sup.- epitaxial growth layer and n.sup.+ buried layer to reach a predetermined depth of p.sup.- silicon substrate is formed under through hole. A first insulating layer covers the internal wall of trench. A covering layer covers the sidewall of through hole. A filling layer is formed to fill trench so that the top surface thereof is located within through hole. A second insulating layer is formed on filling layer.
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