发明授权
US5541799A Reducing the natural current limit in a power MOS device by reducing the
gate-source voltage
失效
通过降低栅源电压降低功率MOS器件的自然电流限制
- 专利标题: Reducing the natural current limit in a power MOS device by reducing the gate-source voltage
- 专利标题(中): 通过降低栅源电压降低功率MOS器件的自然电流限制
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申请号: US265609申请日: 1994-06-24
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公开(公告)号: US5541799A公开(公告)日: 1996-07-30
- 发明人: Thomas A. Schmidt , Ross E. Teggatz , Joseph A. Devore
- 申请人: Thomas A. Schmidt , Ross E. Teggatz , Joseph A. Devore
- 申请人地址: TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: TX Dallas
- 主分类号: H03K17/082
- IPC分类号: H03K17/082 ; H02H7/10
摘要:
In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
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