公开(公告)号：US07554309B2

公开(公告)日：2009-06-30

申请号：US11132750

申请日：2005-05-18

Applicant: John H. Carpenter, Jr. ,  Brett J. Thompsen ,  Benjamin L. Amey ,  Zhihong You ,  Joseph A. Devore

Inventor： John H. Carpenter, Jr. ,  Brett J. Thompsen ,  Benjamin L. Amey ,  Zhihong You ,  Joseph A. Devore

IPC: G05F1/40

CPC classification number: G05F1/618

Abstract: Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.

Abstract translation: 用于调节器最小负载控制的系统，方法和电路。 在一个特定情况下，提供了包括负载控制电路和开关负载的系统。 负载控制电路包括参考电流和代表负载电流的感测电流。 此外，负载控制电路包括响应于参考电流和感测电流之间的比较来驱动控制信号的比较器电路。 开关负载电耦合到负载电压信号以向负载电压信号提供负载。 切换负载可操作以响应于控制信号而在第一负载系数和第二负载系数之间切换。

公开(公告)号：US06407626B1

公开(公告)日：2002-06-18

申请号：US09715759

申请日：2000-11-17

Applicant: John H. Carpenter, Jr. ,  Joseph A. Devore ,  Tohru Tanaka ,  Ross E. Teggatz

Inventor： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Tohru Tanaka ,  Ross E. Teggatz

IPC: H03K500

CPC classification number: H03K5/1252 ,  H03K5/082

Abstract: Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.

Abstract translation: 提供了使用单个比较器的对称滤波器。 除了分压器，电流调节器和比较器之外，本发明的滤波器还提供控制逻辑，其接通或断开上拉开关和/或下拉开关以便完全充电或完全放电电容器。 因此，一方面，本发明是用于对称滤波器的控制逻辑。 此外，提供定时逻辑以提供更严格的对称滤波器性能。

公开(公告)号：US06373343B1

公开(公告)日：2002-04-16

申请号：US09649367

申请日：2000-08-28

Applicant: David J. Baldwin ,  Christopher M. Cooper ,  Joseph A. Devore ,  Ross E. Teggatz

Inventor： David J. Baldwin ,  Christopher M. Cooper ,  Joseph A. Devore ,  Ross E. Teggatz

IPC: H03B524

CPC classification number: H03K3/0231

Abstract: An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.

Abstract translation: 公开了一种集成电路（10），其包括基频振荡器，其包括其电压在高阈值和低阈值之间变化的参考节点（32）。 基频振荡器可操作以在第一输出节点（36）上产生基频处的第一输出。 集成电路（10）还包括耦合到参考节点的电路（C2）。 电路（C2）可操作以感测参考节点（32）处的电压，以确定电压何时超过高阈值和低阈值之间的中间阈值，并响应于该确定产生第二输出。 集成电路（10）还包括耦合到电路（C2）的逻辑（40）和耦合到逻辑（40）的负载电路（50）。 逻辑（40）可操作以响应于第二输出和第一输出而以大于基频的输出频率产生输出信号。

公开(公告)号：US06215637B1

公开(公告)日：2001-04-10

申请号：US09290283

申请日：1999-04-13

Applicant: Ross E. Teggatz ,  John H. Carpenter, Jr. ,  Tohru Tanaka ,  Joseph A. Devore

Inventor： Ross E. Teggatz ,  John H. Carpenter, Jr. ,  Tohru Tanaka ,  Joseph A. Devore

IPC: H02H322

CPC classification number: H01L27/0259

Abstract: A internal circuitry protection scheme which protects on-IC circuitry when an external pin is shorted to a higher than normal voltage. The disclosed solution eliminates cross-talk due to a parasitic NPN.

Abstract translation: 内部电路保护方案，当外部引脚短路到高于正常电压时，保护IC上的电路。 所公开的解决方案消除了由于寄生NPN引起的串扰。

公开(公告)号：US5793245A

公开(公告)日：1998-08-11

申请号：US731629

申请日：1996-10-15

Applicant: Andrew Marshall ,  Joseph A. Devore ,  Raymond T. Summerlin

Inventor： Andrew Marshall ,  Joseph A. Devore ,  Raymond T. Summerlin

IPC: H03K17/16

CPC classification number: H03K17/162

Abstract: A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory transients ("ringing"), along with its associated voltage spikes at the associated output transistor source, can be avoided. Such transients and their associated voltages are avoided by clamping the gate-source voltage on the circuit's output NMOS transistor over the entire positive operation voltage range.

Abstract translation: 提供了一种开关模式调节器电路，以便以基本上功率无损的方式从一个电压电平转换到另一个电压电平。 该电路在电源可以以不连续模式工作的情况下是特别有利的，因为可以避免电感器 - 电容器振荡瞬变（“振铃”）连同其相关联的输出晶体管源处的相关电压尖峰。 通过在整个正工作电压范围内将栅极 - 源极电压钳位在电路的输出NMOS晶体管上来避免这种瞬变及其相关电压。

公开(公告)号：US5579193A

公开(公告)日：1996-11-26

申请号：US486926

申请日：1995-06-07

Applicant: Thomas A. Schmidt ,  Ross E. Teggatz ,  Joseph A. Devore

Inventor： Thomas A. Schmidt ,  Ross E. Teggatz ,  Joseph A. Devore

IPC: H03K17/082 ,  H02H7/10

CPC classification number: H03K17/0822

Abstract: In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, sensing circuitry 30 to sense a predetermined trigger current, and limitation circuitry 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.

Abstract translation: 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，检测电路30以感测预定的触发电流，以及限制电路20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。

公开(公告)号：US06373094B1

公开(公告)日：2002-04-16

申请号：US09908024

申请日：2001-07-18

Applicant: Andrew Marshall ,  Joseph A. Devore ,  Ross E. Teggatz ,  Wayne T. Chen ,  Ricky D. Jordanger

Inventor： Andrew Marshall ,  Joseph A. Devore ,  Ross E. Teggatz ,  Wayne T. Chen ,  Ricky D. Jordanger

IPC: H01L29788

Abstract: An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20). The diffusion region (24 or 26) provides a source of charge for placement on the floating gate layer (22) when programming the EEPROM cell (10).

公开(公告)号：US5812006A

公开(公告)日：1998-09-22

申请号：US739375

申请日：1996-10-29

Applicant: Ross E. Teggatz ,  Joseph A. Devore ,  Kenneth G. Buss ,  Thomas A. Schmidt ,  Taylor R. Efland ,  Stephen C. Kwan

Inventor： Ross E. Teggatz ,  Joseph A. Devore ,  Kenneth G. Buss ,  Thomas A. Schmidt ,  Taylor R. Efland ,  Stephen C. Kwan

IPC: H03K17/06 ,  H03K17/082 ,  H03K5/08

CPC classification number: H03K17/063 ,  H03K17/0822

Abstract: An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.

Abstract translation: 优化的功率输出钳位结构包括具有第一击穿电压的功率输出晶体管和具有耦合到功率输出晶体管的第二击穿电压的击穿结构。 第二击穿电压小于第一击穿电压，并且遵循所有温度和半导体工艺变化的第一击穿电压。 该特征允许降低击穿电压保护带并增加输出结构的可靠性。 还公开了一种保护电路免受感应回扫的方法。 该方法包括以下步骤：利用驱动电路驱动感性负载，关闭感性负载，以及钳位感应电压，电压幅度保护驱动电路不受所有温度和处理变化的影响。

公开(公告)号：US5675241A

公开(公告)日：1997-10-07

申请号：US672125

申请日：1996-06-27

Applicant: Ross E. Teggatz ,  Joseph A. Devore ,  Jonathan R. Knight

Inventor： Ross E. Teggatz ,  Joseph A. Devore ,  Jonathan R. Knight

IPC: G05F3/24 ,  G05F1/56 ,  G05F5/00

CPC classification number: G05F3/247

Abstract: A circuit and method for providing a low drop out voltage regulator. A source follower circuit is provided having a transistor (MD1) with an output terminal for driving a load at its source terminal and a voltage supply coupled to the drain terminal. At least one diode (D1) is coupled between the gate terminal and a ground reference to provide a predetermined voltage at the gate of the transistor (MD1). A voltage multiplier circuit is provided having an input (IN) for receiving an oscillating input voltage and a charge storage device (39) coupled between the oscillating input and a voltage reference (Vref), and being further coupled in series with the voltage reference and then to the gate terminal of the transistor (MD1). The oscillating input voltage is used to charge the charge storage device (39) to a voltage approximately equal to the voltage reference. When the supply voltage falls below the normal level, the series combination of the voltage reference and the charge storage device provides a multiplied voltage at the gate of the transistor, for example a voltage of twice the reference voltage. This high gate voltage keeps the output at the source of the transistor at a high voltage that is approximately equal to the supply voltage, such that the circuit provides a low drop out voltage under low supply voltage conditions.

Abstract translation: 一种用于提供低压降稳压器的电路和方法。 源极跟随器电路具有晶体管（MD1），其具有用于驱动其源极端子处的负载的输出端子和耦合到漏极端子的电压源。 至少一个二极管（D1）耦合在栅极端子和接地基准之间，以在晶体管（MD1）的栅极处提供预定的电压。 提供了具有用于接收振荡输入电压的输入（IN）和耦合在振荡输入和电压参考（Vref）之间的电荷存储装置（39）的电压倍增器电路，并进一步与电压基准串联耦合， 然后到晶体管（MD1）的栅极端子。 振荡输入电压用于将电荷存储装置（39）充电至大致等于电压基准的电压。 当电源电压低于正常电平时，电压基准和电荷存储装置的串联组合在晶体管的栅极处提供倍增电压，例如两倍于参考电压的电压。 该高栅极电压将晶体管源极处的输出保持在大致等于电源电压的高电压，使得该电路在低电源电压条件下提供低压降电压。

公开(公告)号：US06940131B2

公开(公告)日：2005-09-06

申请号：US10609920

申请日：2003-06-30

Applicant: David John Baldwin ,  Joseph A. Devore ,  Robert Steinhoff ,  Jonathan Brodsky

Inventor： David John Baldwin ,  Joseph A. Devore ,  Robert Steinhoff ,  Jonathan Brodsky

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L23/62

CPC classification number: H01L29/0692 ,  H01L27/0266 ,  H01L29/4238

Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).

Abstract translation: 本发明包括具有形成在基板（102）内的P型基板（102）和N型漏极区（104）的MOS器件（100）。 环形N型源极区域（106）通常围绕漏极区域（104）。 源极区域（106）用作MOS器件（100）的源极和用于静电放电保护电路的牺牲集电极保护环。 环形栅极区域（110）通常围绕漏极区域（104）并且与漏极区域（104）电绝缘并且电连接到源极区域（106）。 环形P型体区域（108）通常围绕源极区域（106）并且电连接到源极区域（106）。