发明授权
- 专利标题: Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module
- 专利标题(中): 使用二维多芯片模块的集成电路芯片之间的逻辑三维互连
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申请号: US536076申请日: 1995-09-29
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公开(公告)号: US5543640A公开(公告)日: 1996-08-06
- 发明人: James Sutherland , Timothy L. Garverick , Hem P. Takiar , George F. Reyling, Jr.
- 申请人: James Sutherland , Timothy L. Garverick , Hem P. Takiar , George F. Reyling, Jr.
- 申请人地址: CA Santa Clara
- 专利权人: National Semiconductor Corporation
- 当前专利权人: National Semiconductor Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: H01L23/538
- IPC分类号: H01L23/538 ; H01L25/065 ; H01L27/02 ; H03K19/177 ; H01L27/10
摘要:
A high capacity gate array which incorporates an effectively three dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel. This has the effect of producing a three dimensional interconnect network from a two dimensional arrangement of arrays or chips in a MCM package. The result is a high gate capacity logic device having an increased degree of gate utilization and shortened average interconnect distances, thereby enabling the production of complex devices which have a faster operating speed.