发明授权
US5544340A Method and system for controlling cache memory with a storage buffer to
increase throughput of a write operation to the cache memory
失效
用于利用存储缓冲器来控制高速缓冲存储器以增加对高速缓冲存储器的写入操作的吞吐量的方法和系统
- 专利标题： Method and system for controlling cache memory with a storage buffer to increase throughput of a write operation to the cache memory
- 专利标题（中）： 用于利用存储缓冲器来控制高速缓冲存储器以增加对高速缓冲存储器的写入操作的吞吐量的方法和系统
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申请号： US362755申请日： 1994-12-22
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公开(公告)号： US5544340A公开(公告)日： 1996-08-06
- 发明人: Toshio Doi , Takehisa Hayashi , Kenichi Ishibashi , Takeshi Takemoto
- 申请人： Toshio Doi , Takehisa Hayashi , Kenichi Ishibashi , Takeshi Takemoto
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX2-141484 19900601
- 主分类号： G06F12/08
- IPC分类号： G06F12/08
摘要：
A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.