公开(公告)号：US5544340A

公开(公告)日：1996-08-06

申请号：US362755

申请日：1994-12-22

申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

IPC分类号： G06F12/08

CPC分类号： G06F12/0886

摘要： A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

摘要翻译： 一种控制设置在CPU和主存储器之间的高速缓冲存储器的方法，其中将要写入高速缓冲存储器的数据和地址对存储在缓冲存储器中。 处理从缓冲存储器读取的多对数据和地址，以比较其地址字段。 基于比较的结果，确定了将数据写入高速缓冲存储器中的写入控制，其被细分为多个存储体。 结果，将多对数据和地址写入高速缓冲存储器的多个组，各对的地址彼此不同。 通过上述规定，可以对高速缓冲存储器的每一组独立地进行写入操作，从而提高写入吞吐量。

公开(公告)号：US5223733A

公开(公告)日：1993-06-29

申请号：US793296

申请日：1991-11-14

申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Mitsuo Asai

发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Mitsuo Asai

IPC分类号： H01L23/522 ,  H01L27/02

CPC分类号： H01L23/5225 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A semiconductor integrated circuit device is provided which include a plurality of cell columns each having a number of unit cells previously fabricated on a semiconductor substrate selected from the plural kinds of unit cells which are formed in desired circuits by electrically connecting circuit devices previously arranged. Each column includes at least one kind of unit cell of a dynamic circuit which has a node in a floating state during the operation of the cell unit. A fixed potential shield layer is also provided on the cell columns so as to cover the nodes of the dynamic circuits. By virtue of this, a wiring area for electrically connecting the desired cell units can be located between the cell columns and above the shield layer. In other words, signal wirings in the wiring area can pass over the nodes of the dynamic circuits. without adverse parasitic effects. The unit cell can also be provided with a precharge circuit comprising a standard cell and an in-cell wiring layer. Further, clock input terminals of the unit cells which are provided with a precharge circuit can be divided into plural groups, with all of said clock input terminals belonging to the same group and having equal load capacitances being connected. Clock buffer cells can be provided for supplying clock signals to the clock signal wirings for each group.

摘要翻译： 提供了一种半导体集成电路器件，其包括多个单元列，每个单元列具有预先制造在半导体衬底上的多个单元电池，半导体衬底选自通过电连接先前布置的电路元件而形成在期望电路中的多种单元电池。 每列包括在单元单元的操作期间具有处于浮置状态的节点的动态电路的至少一种单元。 固定电位屏蔽层也设置在单元列上，以覆盖动态电路的节点。 由此，用于电连接所需单元单元的布线区域可以位于单元列之间并且位于屏蔽层之上。 换句话说，布线区域中的信号布线可以通过动态电路的节点。 无不良寄生效应。 单元电池还可以设置有包括标准单元和单元内布线层的预充电电路。 此外，设置有预充电电路的单元电池的时钟输入端子可以被分成多组，所有的所述时钟输入端子都属于同一组并具有相等的负载电容。 可以提供时钟缓冲单元，用于将时钟信号提供给每个组的时钟信号布线。

公开(公告)号：US5087829A

公开(公告)日：1992-02-11

申请号：US443503

申请日：1989-12-01

申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

IPC分类号： H03K5/15

CPC分类号： H03K5/15

摘要： This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

摘要翻译： 本发明公开了一种时钟分配系统，其将作为基准时钟的第一时钟信号作为相位和频率的参考分配给每个处理单元（例如，LSI），并且通过以下方式生成要在每个处理单元中使用的多相第二时钟信号： 延迟时间被调整的延迟电路组。 时钟分配系统包括用于产生单相参考时钟的时钟产生模块; 第一控制环路，用于将参考时钟的相位与反馈信号的相位进行比较，并且调整参考时钟的相位，使得它们的相位一致; 以及包括由多个可变延迟电路组成的延迟电路组的第二控制回路，所述多个可变延迟电路输入由第一控制回路相位调整的参考时钟并串联连接的参考时钟，以及用于产生多相时钟信号的装置 通过使用多个可变延迟电路中的每一个的输出信号和相位调整参考时钟，控制多个可变延迟电路的延迟时间，以便与相位调整参考的周期完成预定的关系 时钟，并将多相时钟信号中的一个作为上述反馈信号施加到第一控制回路。

公开(公告)号：US4950925A

公开(公告)日：1990-08-21

申请号：US246196

申请日：1988-09-19

申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi

发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi

IPC分类号： H03K17/567 ,  H03K19/017 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/096

CPC分类号： H03K19/01721 ,  H03K19/01742 ,  H03K19/09448

摘要： An output signal of a logic portion is inputted to the gate of FET inside an output buffer portion to inverse the signal polarity by this FET and is outputted through a bipolar transistor effecting an emitter follower operation or the like. An FET controlled by a clock signal is disposed between the base of the bipolar transistor and the ground and an FET which is turned ON during a pre-charge operation and when the bipolar transistor is OFF during logic calculation is disposed between the emitter and the ground so as to short-circuit the emitter and the ground during the pre-charge operation. In this manner, higher operation speed, higher integration density and high operation margin can be accomplished without losing the characteristic features of a Bi-CMOS dynamic logic circuit in its high operation speed and low power dissipation.

摘要翻译： 逻辑部分的输出信号被输入到输出缓冲器部分内的FET的栅极，以通过该FET反转信号极性，并通过实现射极跟随器操作等的双极晶体管输出。 由时钟信号控制的FET设置在双极晶体管的基极和地之间，在预充电操作期间被接通的FET和在逻辑运算期间当双极晶体管截止时被布置在发射极和地之间 以便在预充电操作期间短路发射极和地。 以这种方式，可以实现更高的操作速度，更高的集成密度和高的操作裕度，而不会在其高操作速度和低功耗中丧失Bi-CMOS动态逻辑电路的特征。

公开(公告)号：US5065048A

公开(公告)日：1991-11-12

申请号：US397199

申请日：1989-08-23

申请人： Mitsuo Asai ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

发明人： Mitsuo Asai ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

IPC分类号： H03K19/003 ,  H03K19/096

CPC分类号： H03K19/0963 ,  H03K19/00338

摘要： A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.

摘要翻译： 一种动态半导体逻辑电路，包括：MOS FET逻辑部分，用于响应输入模式预充电之后的输入逻辑信号和所述逻辑部分的内部节点进行高速逻辑运算; CMOS / BiCMOS输出缓冲器部分，用于输出 逻辑运算，以及噪声抑制部，用于防止误操作而不牺牲高速运行特性。 该电路采用0.5μm规则技术制造，并且在4.5 V或更低的低压电源下以高速运行，具有预充电部分，用于对MOS FET逻辑部分的输出节点和内部节点进行预充电 以及噪声抑制部分，用于通过反馈输出缓冲器部分的输出来将逻辑部分的输出节点锁存到源极电位，以便放大软误差容限。 闭锁电流保持在小于预定比率以保持高速操作特性。

公开(公告)号：US5794020A

公开(公告)日：1998-08-11

申请号：US663982

申请日：1996-06-14

申请人： Akira Tanaka ,  Toshio Doi ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

发明人： Akira Tanaka ,  Toshio Doi ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

IPC分类号： H04L7/00 ,  G06F1/12 ,  H04L7/02 ,  H04L7/033 ,  H04L7/08

CPC分类号： H04L7/0337 ,  H04L7/0008 ,  H04L7/0041

摘要： A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin. In a normal operation, the judging circuit detects a deviation from the optimum point and the delay amount of the first variable delay circuit is finely adjusted in accordance with the detection, thereby maintaining the latch timing of the reception data at the optimum point.

摘要翻译： 第一可变延迟电路延迟从输入缓冲器输出的发送单元的接收数据，并将延迟的数据生成到数据未识别时间检测部分。 第一和第二锁存器分别在第三锁存器的锁存定时之前和之后以规则的间隔分别具有第二和第三可变延迟电路接收和输出的锁存定时。 在调整操作中，第二和第三可变延迟电路的延迟量被固定为足够小于传送周期的值，可变延迟电路的延迟量增加，判断电路检测到接收的前一边缘 数据，随后，第二和第三可变延迟电路的延迟量依次增加同时保持相同的值，并且检测接收数据的后沿。 在这种情况下，第三锁存器的定时被设置为最大裕量的最佳点。 在正常操作中，判断电路检测到与最佳点的偏差，并且根据检测精细地调整第一可变延迟电路的延迟量，从而将接收数据的锁存定时保持在最佳点。

公开(公告)号：US5165010A

公开(公告)日：1992-11-17

申请号：US461080

申请日：1990-01-04

申请人： Noboru Masuda ,  Moritoshi Yasunaga ,  Minoru Yamada ,  Akira Masaki ,  Mitsuo Asai ,  Yuzo Hirai ,  Masayoshi Yagyu ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

发明人： Noboru Masuda ,  Moritoshi Yasunaga ,  Minoru Yamada ,  Akira Masaki ,  Mitsuo Asai ,  Yuzo Hirai ,  Masayoshi Yagyu ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06N3/04

摘要： An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

公开(公告)号：US5043990A

公开(公告)日：1991-08-27

申请号：US279034

申请日：1988-12-02

申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi

发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi

IPC分类号： G06F7/00 ,  G06F11/10 ,  G06F11/16

CPC分类号： G06F11/1641 ,  G06F11/10 ,  G06F7/57

摘要： A semiconductor integrated circuit device is provided which includes a logic circuit utilizing an error detection code. The device has a first circuit train including a series connection of plural stages of operation circuits for receiving input data, performing predetermined operations while the input data propagates through the operation circuits and providing output data; a second circuit train including a series connection of plural stages of error detection code correction circuits for receiving error detection code input corresponding to the input data, applying corrections to the error detection code in correspondence to the operations in the operation circuits in the first circuit train, and outputting an error detection code corresponding to the output data; and at least one error detection circuit for performing a comparison and check of the output of the operation circuit in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train. Also, the semiconductor integrated circuit device of this invention comprises a logic circuit incorporating therein an error detection function by doubling the circuits which comprise a logic circuit using the error detection code, doubled operation circuits having the same function and inputted with the same signal, and a comparison circuit for mutually comparing the outputs of the doubled operation circuits.

摘要翻译： 提供一种半导体集成电路器件，其包括利用错误检测码的逻辑电路。 该装置具有第一电路列，其包括用于接收输入数据的多级操作电路的串联连接，当输入数据通过操作电路传播并提供输出数据时执行预定操作; 包括多级错误检测码校正电路的串联连接的第二电路列，用于接收对应于输入数据的错误检测码输入，对应于第一电路列中的操作电路中的操作对错误检测码进行校正 并且输出与所述输出数据相对应的错误检测码; 以及至少一个误差检测电路，用于对第一电路列中的运算电路的输出和第二电路列中相应的检错码校正电路的输出进行比较和检查。 此外，本发明的半导体集成电路器件包括一个逻辑电路，其中结合有误差检测功能，通过使用误差检测码将包括逻辑电路的电路加倍，具有相同功能的双倍运算电路并输入相同的信号，以及 比较电路，用于相互比较双重运算电路的输出。

公开(公告)号：US4849660A

公开(公告)日：1989-07-18

申请号：US201961

申请日：1988-06-03

申请人： Takehisa Hayashi ,  Kenichi Ishibashi ,  Toshio Doi

发明人： Takehisa Hayashi ,  Kenichi Ishibashi ,  Toshio Doi

IPC分类号： H03K19/0175 ,  H03K19/0944

CPC分类号： H03K19/017518 ,  H03K19/09448

摘要： An output interface circuit comprises a CMOS circuit including a pair of complementary MOS transistors and receiving an input signal at the gates of the paired MOS transistors, a bipolar transistor having its base connected to the output of the CMOS circuit and its emitter from which an output signal is delivered, and a control circuit connected between the paired MOS transistors and operable, upon the fall of the output signal, to cut off a current flowing through any one of the paired MOS transistors so as to control the low level at the output of the CMOS circuit such that the low level does not fall before a potential level by which the low level of the output signal is permitted to be at a desirable predetermined potential level. Specifically, the CMOS circuit includes a pair of complementary MOS transistors comprised of a P-type MOS transistor and an N-type MOS transistor and receives an input signal of CMOS level to operate in inverter fashion. The bipolar transistor connected to the output of the CMOS circuit operates as an emitter follower to deliver an output signal of ECL level. Upon the fall of the output signal, the control circuit operates to cut off a current flowing through the N-type MOS transistor so as to control the low level at the output of the CMOS circuit such that the low level does not fall below a level which is about 0.5 to 0.8 volts higher than the low level of the output signal (ECL level) of the bipolar transistor.

摘要翻译： 输出接口电路包括CMOS电路，其包括一对互补MOS晶体管，并在所述成对MOS晶体管的栅极处接收输入信号;双极晶体管，其基极连接到CMOS电路的输出端及其发射极， 信号被输送，以及控制电路，连接在成对的MOS晶体管之间，并且在输出信号的下降时可以切断流过成对的MOS晶体管中的任何一个的电流，以便控制在输出端的低电平 CMOS电路使得低电平不会落在允许输出信号的低电平处于期望的预定电位电平的电位电平之前。 具体地说，CMOS电路包括由P型MOS晶体管和N型MOS晶体管组成的一对互补MOS晶体管，并接收CMOS电平的输入信号以逆变器方式工作。 连接到CMOS电路的输出的双极晶体管用作射极跟随器来传送ECL电平的输出信号。 在输出信号的下降时，控制电路工作以切断流过N型MOS晶体管的电流，以便控制CMOS电路的输出处的低电平，使得低电平不低于电平 其比双极晶体管的输出信号（ECL电平）的低电平高约0.5至0.8伏。

公开(公告)号：US06049221A

公开(公告)日：2000-04-11

申请号：US111804

申请日：1998-07-08

申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  H03K19/175

CPC分类号： H03K19/0005

摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

摘要翻译： 具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。 当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。 如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。 当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值 并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。