发明授权
- 专利标题: Digital phase locked loop circuit
- 专利标题(中): 数字锁相环电路
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申请号: US316463申请日: 1994-09-30
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公开(公告)号: US5552727A公开(公告)日: 1996-09-03
- 发明人: Yuichi Nakao
- 申请人: Yuichi Nakao
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX5-250429 19931006
- 主分类号: H03L7/14
- IPC分类号: H03L7/14 ; H03L7/189 ; H03K5/159
摘要:
A digital circuit apparatus having an A/D converter for digitalizing a control voltage which determines the oscillation frequency of an internal clock outputted from a voltage-controlled oscillator, a storing unit for holding a digitalized value, a D/A converter with corrective function for correcting the digital value being held and subjecting the corrected digital value to D/A conversion, and a lock detector for detecting the matching in phase of the internal clock and an external clock. Phase information obtained when the internal clock and the external clock match in phase is held so that, when the generation of the internal clock outputted from the voltage-controlled oscillator is halted and then resumed, the matching in phase of the external clock and internal clock can be achieved in a short period of time.
公开/授权文献
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