Comprising a data memory region (21) for data and pointer memory sections (23) for pointers controlling transfer of the data to or from an I/O device for a CPU, a memory (13) for DMA comprises in each pointer memory section a one-bit memory area for a discrimination or skip bit (Bi) indicative of whether the transfer should proceed or be skipped at one of the data that is controlled by the pointer stored in the pointer memory section under consideration. Preferably, the discrimination bit represents binary zero and one values when the transfer should proceed and be skilled, respectively. It is preferred to form a DMA controller together with the memory in an LSI semiconductor device.