A non-volatile split-gate memory cell 8 which can be programmed with only a five volt power supply and is fabricated using standard transistor processing methods, comprises a semiconductor substrate 10 with a source 12 and a drain 14 region separated by a channel region 16. A conductive floating gate 18 is formed over a portion 16a of the channel region 16 and separated by a FAMOS oxide 20. A conductive control gate 22 is formed over but electrically insulated from the floating gate 18 and over a second portion 16b of the channel region 16. The control gate 22 is separated from the second portion of the channel 16b by a pass oxide 26 which is thicker than the FAMOS oxide 20. Other embodiments and processes are also disclosed.