发明授权
US5565766A Semiconductor circuit element device with arrangement for testing the
device and method of test
失效
具有用于测试装置和测试方法的装置的半导体电路元件装置
- 专利标题: Semiconductor circuit element device with arrangement for testing the device and method of test
- 专利标题(中): 具有用于测试装置和测试方法的装置的半导体电路元件装置
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申请号: US952651申请日: 1992-09-28
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公开(公告)号: US5565766A公开(公告)日: 1996-10-15
- 发明人: Hiroichi Kuwahara , Kiyoyuki Yoshida , Kazuyuki Iida
- 申请人: Hiroichi Kuwahara , Kiyoyuki Yoshida , Kazuyuki Iida
- 申请人地址: JPX Kanagawa
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kanagawa
- 优先权: JPX3-251074 19910930
- 主分类号: G01R31/28
- IPC分类号: G01R31/28 ; G01R31/3185 ; G01R31/02 ; G06F11/22
摘要:
A semiconductor circuit element device with an arrangement for testing the device including a plurality of first logic circuits provided in correspondence with internal line groups which are formed by grouping the internal lines into a plurality of groups, a plurality of internal lines belonging to a group in question constituting the input lines of the plurality of first logic circuits, for outputting an active output signal when all of the inputs represent active signals and outputting an inactive output signal when at least one of the inputs represents an inactive signal; and a second logic circuit constituted by one or more stages of circuit structures, for receiving the outputs of the first logic circuits and sending out an output signal such that the output signal in the case where all of the inputs are inactive output signals is different from the output signal in the case where at least one of the inputs is an active output signal.
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