- 专利标题: Signal output circuit operating stably and arrangement of power supply interconnection line therefor in semiconductor integrated circuit device
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申请号: US352021申请日: 1994-11-30
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公开(公告)号: US5574397A公开(公告)日: 1996-11-12
- 发明人: Shigeki Tomishima , Hideto Hidaka , Masakazu Hirose , Takahiro Tsuruda
- 申请人: Shigeki Tomishima , Hideto Hidaka , Masakazu Hirose , Takahiro Tsuruda
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX4-291136 19921029
- 主分类号: H01L21/822
- IPC分类号: H01L21/822 ; G11C5/14 ; G11C7/10 ; G11C11/401 ; G11C11/409 ; H01L21/82 ; H01L27/04 ; H03K17/16 ; H03K19/0175 ; H01J19/82
摘要:
A semiconductor integrated circuit device includes a pad receiving a power supply potential and a pad receiving a ground potential both formed on a chip, and a power supply potential line and a ground potential line connected to respective pads and formed in a loop manner along a circumference of the chip. The semiconductor integrated circuit device includes a first data output circuit provided for a data output terminal proximate to a predetermined potential pad, and a second data output circuit provided for a data output terminal distant from the predetermined potential pad. First and second data output circuits drive corresponding data output terminals to the predetermined potential in two steps at a lower rate and a higher rate in accordance with an internal output data signal. First and second data output circuits include components for compensating for and canceling an influence on driving the corresponding output nodes due to the difference of distances to the predetermined pad therefrom. As a result, data is provided at a high speed and without overshoot, undershoot or ringing.
公开/授权文献
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