A memory device, which communicates with external address and data buses, includes a circuit for mapping a redundant memory column having a redundant memory cell to an address of a defective memory column. An enable line communicates with the redundant memory column and selectively carries active and inactive signal levels for respectively enabling and disabling communication between the data bus and the redundant memory cell. An address decoder receives an address signal on the address bus and generates the active level on the enable line when the value of the address signal equals the address of the defective memory cell. A driver precharges the enable line to the inactive level while the address signal is invalid.