A synchronized semiconductor memory device comprising a memory cell array, an address input circuit, an address set circuit, a command input circuit, a data reading/writing control circuit, a data output circuit, a data input circuit, a clock input circuit, an internal clock generating circuit, an internal clock timing control circuit. The clock input circuit comprises first and second clock input circuits, and the internal clock generating circuit comprises a first internal clock generating circuit receiving a clock information from the first clock input circuit, for generating a fist reference internal clock signal controlling the address input circuit, the address set circuit, the command input circuit, the data reading/writing control circuit, the data output circuit and the data input circuit, and a second internal clock generating circuit receiving a clock information from the second clock input circuit, for generating a second reference internal clock signal controlling only the data output circuit.