发明授权
US5589405A Method for fabricating VDMOS transistor with improved breakdown
characteristics
失效
用于制造具有改进的击穿特性的VDMOS晶体管的方法
- 专利标题: Method for fabricating VDMOS transistor with improved breakdown characteristics
- 专利标题(中): 用于制造具有改进的击穿特性的VDMOS晶体管的方法
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申请号: US403629申请日: 1995-04-21
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公开(公告)号: US5589405A公开(公告)日: 1996-12-31
- 发明人: Claudio Contiero , Paola Galbiati , Lucia Zullino
- 申请人: Claudio Contiero , Paola Galbiati , Lucia Zullino
- 申请人地址: ITX Agrate Brianza
- 专利权人: SGS-Thomson Microelectronics, S.r.l.
- 当前专利权人: SGS-Thomson Microelectronics, S.r.l.
- 当前专利权人地址: ITX Agrate Brianza
- 优先权: ITXMI92A0344 19920218
- 主分类号: H01L21/765
- IPC分类号: H01L21/765 ; H01L29/06 ; H01L29/40 ; H01L29/78 ; H01L49/00
摘要:
The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.
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