发明授权
US5589701A Process for realizing P-channel MOS transistors having a low threshold
voltage in semiconductor integrated circuits for analog applications
失效
用于实现用于模拟应用的半导体集成电路中具有低阈值电压的P沟道MOS晶体管的工艺
- 专利标题: Process for realizing P-channel MOS transistors having a low threshold voltage in semiconductor integrated circuits for analog applications
- 专利标题(中): 用于实现用于模拟应用的半导体集成电路中具有低阈值电压的P沟道MOS晶体管的工艺
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申请号: US486747申请日: 1995-06-07
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公开(公告)号: US5589701A公开(公告)日: 1996-12-31
- 发明人: Livio Baldi
- 申请人: Livio Baldi
- 申请人地址: ITX Agrate Brianza
- 专利权人: SGS-Thomson Microelectronics S.r.1.
- 当前专利权人: SGS-Thomson Microelectronics S.r.1.
- 当前专利权人地址: ITX Agrate Brianza
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238 ; H01L29/76
摘要:
A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.
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