A method was achieved for making electrical connections to FET self-aligned source/drain areas extending the limits of the photolithographic resolution and relaxing the alignment tolerance. FET gate electrodes are formed by patterning a first polysilicon layer having a first insulating layer thereon. Lightly doped drains (LDDs) and insulating first sidewall spacers are then formed. A polycide layer (second polysilicon/silicide layer) having a second insulating thereon is then deposited and patterned. The new method involves etching the second insulating layer and partially into the polycide layer. After removing the photoresist, another dielectric layer is conformally deposited and then anisotropically etched back to form the second sidewall spacers. The remaining polycide layer is then etched using the second insulating layer and the second spacer as a hard mask. Thus, second poly extensions are formed over and onto the first poly and the field oxide. Using this new process, both the second polysilicon layer and the contact layer become alignment insensitive and silicon trenches, caused by misalignment, cannot occur. Furthermore, a minimum gate length, a minimum gate to FOX spacing and a minimum FOX isolation width can be achieved with the existing 0.35 um process technology.