发明授权
- 专利标题: Two input-two output differential latch circuit
- 专利标题(中): 两路输入二输出差分锁存电路
-
申请号: US557556申请日: 1995-11-14
-
公开(公告)号: US5625308A公开(公告)日: 1997-04-29
- 发明人: Osamu Matsumoto , Takahiro Miki , Toshio Kumamoto
- 申请人: Osamu Matsumoto , Takahiro Miki , Toshio Kumamoto
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX7-141788 19950608
- 主分类号: H03M1/34
- IPC分类号: H03M1/34 ; H03K3/0233 ; H03K3/356 ; H03K3/289
摘要:
A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.
公开/授权文献
- US5448591A Method and apparatus for clock and data delivery on a bus 公开/授权日:1995-09-05