公开(公告)号：US5625308A

公开(公告)日：1997-04-29

申请号：US557556

申请日：1995-11-14

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03M1/34 ,  H03K3/0233 ,  H03K3/356 ,  H03K3/289

CPC分类号： H03K3/35606 ,  H03K3/356034 ,  H03K3/35613

摘要： A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.

摘要翻译： 一种高性能差分锁存电路，包括由用作恒流源的NMOS晶体管（27），PMOS晶体管（3,4）和NMOS晶体管（23,24）组成的差分放大器电路，由NMOS 晶体管（25,26）以及由NMOS晶体管（21,22,28）组成的用于交替操作差分放大功能和锁存功能的开关电路，用作恒流源的晶体管（27）具有直接连接的漏极端子 到晶体管（23,24）和直接连接到接地电压（2）的源极端子，由此差分锁存电路在差分放大期间不损失恒定电流源功能而差分放大信号。

公开(公告)号：US5629700A

公开(公告)日：1997-05-13

申请号：US552016

申请日：1995-11-02

申请人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/44 ,  H03M1/34

CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/069 ,  H03M1/1215 ,  H03M1/167

摘要： An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.

摘要翻译： A / D转换器模块A / D1将模拟输入信号Vin转换为数字信号并输出​​其D / A输出。 第一SH / SUBT7,8以与所述A / D转换相同的定时采样信号Vin和电压VRM，并分别输出相应采样值和保持期间的D / A输出的结果。 减法的结果都是几十mV，不需要考虑差分放大器DIFF11的线性度。 在采样期间，电路SHR1输出从A / D转换器模块A / D1中的梯形电阻器的特定2点取出的每个参考分接电压与电压VRM之间的差分电压，而差分放大器DIFF12施加参考 电压到下一个A / D转换器模块A / D2。 这样的操作在每个阶段进行。 因此，可以使得在第一级中具有优异线性度的任何S / H电路和放大器不必减少电力消耗。

公开(公告)号：US5821893A

公开(公告)日：1998-10-13

申请号：US740520

申请日：1996-10-30

申请人： Toshio Kumamoto ,  Osamu Matsumoto

发明人： Toshio Kumamoto ,  Osamu Matsumoto

IPC分类号： H03M1/14 ,  H03M1/06 ,  H03M1/16 ,  H03M1/38

CPC分类号： H03M1/0695 ,  H03M1/167

摘要： In a pipeline type A/D converter, a switch for sampling an analog potential signal has its other terminal in connection with an A/D converter, a D/A converter, a capacitor for subtraction. Even when frequency of the analog potential signal is raised such that input current is increased and a voltage drop is increased at the switch, there will be no error in the result of subtraction like in the conventional example where analog potential signal was directly input to A/D converter. Accordingly, a pipeline type A/D converter with low power dissipation and satisfactory frequency characteristics is obtained.

摘要翻译： 在流水线型A / D转换器中，用于对模拟电位信号采样的开关具有与A / D转换器，D / A转换器，用于减法的电容器相连的另一端。 即使在模拟电位信号的频率升高使得输入电流增加并且在开关处电压降增加的情况下，与在将模拟电位信号直接输入到A的常规示例中一样，减法结果将不会有误差 / D转换器。 因此，获得具有低功耗和令人满意的频率特性的流水线型A / D转换器。

公开(公告)号：US5966088A

公开(公告)日：1999-10-12

申请号：US982279

申请日：1997-12-01

申请人： Osamu Matsumoto ,  Toshio Kumamoto

发明人： Osamu Matsumoto ,  Toshio Kumamoto

IPC分类号： H03M1/44 ,  H03M1/10 ,  H03M1/16

CPC分类号： H03M1/1023 ,  H03M1/168

摘要： An A/D converter includes a sample-hold circuit, A/D converting stages connected in series to the sample-hold circuit, and an encoder/latch circuit which adds 3-bit digital signals issued from the A/D converting stages to each other for outputting a signal of 9 bits. The sample-hold circuit and the A/D converting stages each include a differential amplifier. Differential outputs of each differential amplifier are short-circuited for a predetermined initial period in each sampling period.

摘要翻译： A / D转换器包括采样保持电路，与采样保持电路串联连接的A / D转换级，以及编码器/锁存电路，其将从A / D转换级发出的3位数字信号加到每个 另一个用于输出9位的信号。 采样保持电路和A / D转换级各自包括差分放大器。 在每个采样周期中，每个差分放大器的差分输出在预定的初始周期短路。

公开(公告)号：US5696511A

公开(公告)日：1997-12-09

申请号：US738585

申请日：1996-10-29

申请人： Osamu Matsumoto ,  Toshio Kumamoto

发明人： Osamu Matsumoto ,  Toshio Kumamoto

IPC分类号： H03M1/10 ,  H03F3/45 ,  H03M1/06 ,  H03M1/12 ,  H03M1/14 ,  H03M1/16 ,  H03M1/42

CPC分类号： H03M1/0695 ,  H03M1/167

摘要： In a pipeline type A/D converter, a sample/hold.cndot.subtracter circuit of an A/D converter block of a first stage samples an analog voltage and outputs an offset voltage at a first phase, and subtracts an output voltage of an A/D converter from the sampled analog voltage in a second phase. An A/D converter of an A/D converter block of a succeeding stage subtracts the output voltage of the sample/hold.cndot.subtracter circuit of the first phase from the output voltage of the sample hold.cndot.subtracter circuit of the second phase, and converts the subtracted result into a digital code. The influence of an offset of a differential amplifier included in the sample/hold.cndot.subtracter circuit is removed so that A/D conversion of high accuracy is allowed.

摘要翻译： 在流水线型A / D转换器中，第一级的A / D转换器模块的采样/保持减法器电路对模拟电压进行采样，并在第一阶段输出偏移电压，并且减去A / D转换器从第二阶段的采样模拟电压。 后级的A / D转换器模块的A / D转换器从第二相的采样保持电路的输出电压中减去第一相的采样/保持电路的输出电压，并将其转换 减去结果成数字代码。 除去包含在采样/保持抑制电路中的差分放大器的偏移的影响，使得允许高精度的A / D转换。

公开(公告)号：US5731776A

公开(公告)日：1998-03-24

申请号：US714423

申请日：1996-09-16

申请人： Toshio Kumamoto ,  Osamu Matsumoto

发明人： Toshio Kumamoto ,  Osamu Matsumoto

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/362

摘要： A ladder resistance (1) consisting of resistance elements (r1, r2, . . . , r8) connected in series with intermediate taps (T1, T2, . . . , T7) interposed is so arranged as to be folded back at its midpoint. Pairs of differential comparators (C1 and C7, C2 and C6, . . . ) which are connected to common intermediate taps are each disposed adjacently so as to be nearest to the intermediate tap to be connected thereto. Accordingly, wires connecting the differential comparators (C1, C2, . . . , C7) to the intermediate taps (T1, T2, . . . , T7) become shorter and an area of a semiconductor chip needed for arranging the wires can be reduced. Thus, reduction in area of the semiconductor chip needed for providing the device therein is achieved.

摘要翻译： 插入与中间抽头（T1，T2，...，T7）串联连接的电阻元件（r1，r2，...，r8）组成的梯形电阻（1）被布置为在其中点 。 连接到公共中间抽头的差分比较器（C1和C7，C2和C6，...）的对相邻设置成最靠近要与其连接的中间抽头。 因此，将差分比较器（C1，C2，... C7）连接到中间抽头（T1，T2，...，T7）的电线变短，并且可以减少布线所需的半导体芯片的面积 。 因此，实现了在其中提供设备所需的半导体芯片的面积减小。

公开(公告)号：US20080024340A1

公开(公告)日：2008-01-31

申请号：US11902773

申请日：2007-09-25

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage−OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于关闭NMOS晶体管M 12 P，M 12 N，M 22 P，M 22 N，M 32 P和M 32 N的截止控制电压（BIAS 3） ON控制电压（BIAS 2）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US20060044169A1

公开(公告)日：2006-03-02

申请号：US11214723

申请日：2005-08-31

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage—OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于在接近ON控制电压（BIAS2）的电压下关断NMOS晶体管M12P，M12N，M22P，M22N，M32P和M32N的OFF控制电压（BIAS3）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US07292172B2

公开(公告)日：2007-11-06

申请号：US11214723

申请日：2005-08-31

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage-OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于关闭NMOS晶体管M 12 P，M 12 N，M 22 P，M 22 N，M 32 P和M 32 N的截止控制电压（BIAS 3） ON控制电压（BIAS 2）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US09457413B2

公开(公告)日：2016-10-04

申请号：US13739766

申请日：2013-01-11

申请人： Osamu Matsumoto ,  Souzou Kawasaki

发明人： Osamu Matsumoto ,  Souzou Kawasaki

IPC分类号： B23C5/08 ,  B23C5/20

CPC分类号： B23C5/207 ,  B23C5/08 ,  B23C5/205 ,  B23C2200/0466 ,  B23C2200/085 ,  B23C2200/367 ,  B23C2210/168 ,  B23C2210/66 ,  B23C2220/36 ,  Y10T407/1906 ,  Y10T407/1942 ,  Y10T407/235

摘要： A cutting insert includes an insert body portion and a plurality of projecting portions provided integrally with the insert body portion. The projecting portion includes a cutting edge and includes projecting portion upper and lower surfaces, two projecting portion side surfaces, and a projecting portion side end surface extending therebetween. In the projecting portion, a round corner surface extends between the projecting portion upper surface and the projecting portion side end surface. The cutting edge is formed so as to include a corner formed along an edge of the round corner surface and such that the projecting portion side surface serves as a rake face. The projecting portion is designed such that a length between the two projecting portion side surfaces is smaller than a diameter of an inscribed circle defined on the insert body portion.

摘要翻译： 切削刀片包括插入件主体部分和与插入件主体部分整体设置的多个突出部分。 突出部分包括切割边缘，并且包括突出部分上表面和下表面，两个突出部分侧表面和在它们之间延伸的突出部分侧端面。 在突出部中，圆角部在突出部上表面与突出部侧端面之间延伸。 切削刃形成为包括沿着圆角的边缘形成的角部，并且突出部侧面用作前刀面。 突出部被设计成使得两个突出部侧表面之间的长度小于限定在插入物主体部分上的内接圆的直径。