发明授权
- 专利标题: Layout methodology, mask set, and patterning method for phase-shifting lithography
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申请号: US542741申请日: 1995-10-13
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公开(公告)号: US5635316A公开(公告)日: 1997-06-03
- 发明人: Giang T. Dao
- 申请人: Giang T. Dao
- 申请人地址: CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G03F1/34
- IPC分类号: G03F1/34 ; G03F7/20 ; G03F9/00
摘要:
A device layer layout methodology, and method and apparatus for patterning a photosensitive layer. Device features are placed on lines running in rows and/or columns during layout. The lines and/or columns are extracted from the database to produce a layout of the phase-edge phase shifting layer. The photosensitive layer may be exposed to a mask corresponding to this layout, to produce latent image of the rows and/or lines. The photosensitive layer is also exposed to the device layer layout to expose unwanted portions of the phase-edge layer. Methods of forming a variety of device features, including contact/via openings and contact/via plugs are disclosed.
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