发明授权
- 专利标题: Fault tolerant multiprocessor computer system
- 专利标题(中): 容错多处理器计算机系统
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申请号: US708965申请日: 1991-05-31
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公开(公告)号: US5649090A公开(公告)日: 1997-07-15
- 发明人: David S. Edwards , William A. Shelly , Jiuyih Chang , Minoru Inoshita , Leonard G. Trubisky
- 申请人: David S. Edwards , William A. Shelly , Jiuyih Chang , Minoru Inoshita , Leonard G. Trubisky
- 申请人地址: MA Billerica
- 专利权人: Bull hn Information Systems Inc.
- 当前专利权人: Bull hn Information Systems Inc.
- 当前专利权人地址: MA Billerica
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; G06F11/10 ; G06F11/14 ; G06F11/22 ; G06F12/08
摘要:
A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.
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