公开(公告)号：US10366299B2

公开(公告)日：2019-07-30

申请号：US13650413

申请日：2012-10-12

申请人： BULL HN INFORMATION SYSTEMS, INC.

发明人： David Lowell Bowne ,  Shahrom Kiani ,  Carlos Macia ,  Russell W. Guenthner

IPC分类号： G06K9/00 ,  G06K9/36

摘要： A scanning camera upgrade adaptor system provides backwards compatibility when an existing scanning camera subsystem is replaced or upgraded in automated sorting equipment with a newer camera having a different data format. The adaptor system allows sorting equipment such as mail sorting equipment to be upgraded or repaired with a new camera while providing compatibility and optional fallback to a previous mode of operation of the existing equipment. The upgrade system enables legacy equipment and newly added sorting/processing equipment to be utilized in conjunction, while reducing cost of upgrade and necessity for completely new equipment as desirable features are added.

公开(公告)号：US20080208562A1

公开(公告)日：2008-08-28

申请号：US12148205

申请日：2008-04-17

申请人： Russell W. Guenthner ,  Sidney L. Andress ,  John Heath

发明人： Russell W. Guenthner ,  Sidney L. Andress ,  John Heath

IPC分类号： G06F9/455

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/30174

摘要： Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

摘要翻译： 提供了用于在主机64位机器上仿真的目标36位机器的指令集的两个唯一指令，以便实现模拟应用程序对存储在存储器中的“包含”字的可见性 主机。 “LOAD64”指令将模拟器存储位置加载到包含字的“正常”36位的模拟“Q”（补充累加器）寄存器中。 同时，64位包含字的“上”28位被复制到表示仿真“A”（累加器）寄存器的仿真器存储单元中。 因此，仿真的36位机器“看到”并且可以检查64位字的整体。 “Store64”指令将模拟的“Q”寄存器内容存储到64位包含字的低36位，同时将模拟的“A”寄存器内容的低28位存储到高位28位 的64位包含字。

公开(公告)号：US07314491B2

公开(公告)日：2008-01-01

申请号：US11025639

申请日：2004-12-29

申请人： Russell W. Guenthner ,  Rodney B. Schultz ,  F. Michel Brown ,  Stefan R. Bohult ,  William J Brophy

发明人： Russell W. Guenthner ,  Rodney B. Schultz ,  F. Michel Brown ,  Stefan R. Bohult ,  William J Brophy

IPC分类号： G06F9/455

CPC分类号： G06F9/45537 ,  Y10S707/99936

摘要： This invention relates to the art of computer system emulation and, more particularly, to a computer system emulator in which the functions normally performed by the hardware in a legacy central processor unit are emulated by a software program. The invention is to enhance the emulated instruction set beyond that of the legacy machine such to include as new single instructions a method for invoking operating system functions, with the machine coding of the operating system functions now being performed by machine code native to the new host machine, rather than as a sequence of emulated legacy instructions.

摘要翻译： 本发明涉及计算机系统仿真技术，更具体地说，涉及一种计算机系统仿真器，其中由传统中央处理器单元中的硬件正常执行的功能由软件程序仿真。 本发明是为了增强仿真指令集超出传统机器的指令集，以便将新的单个指令作为一种用于调用操作系统功能的方法，其中操作系统功能的机器编码现在由原始的机器代码执行 机器，而不是作为仿真遗留指令的序列。

公开(公告)号：US20050246566A1

公开(公告)日：2005-11-03

申请号：US10837079

申请日：2004-04-30

申请人： Stefan Boult

发明人： Stefan Boult

IPC分类号： A01K67/027 ,  A61K38/00 ,  A61K48/00 ,  C07K14/755 ,  C12N15/85 ,  C12N15/861 ,  G06F1/04 ,  G06F1/14

CPC分类号： G06F1/04 ,  A61K38/00 ,  A61K48/00 ,  G06F1/14

摘要： A simple and accurate processor derating method includes: sampling a real-time counter/clock too obtain an initial time value T1; resetting an Icnt Counter; incrementing the Icnt Counter to reflect the processing of each instruction; comparing the count in the Icnt Counter to a predetermined count IcntMax and if the count in the Icnt Counter is at least IcntMax, then sampling the RTC to obtain a second time T2. T1 is then subtracted from T2 to obtain a time difference DT which is multiplied by ((1−1/DF)−1) to obtain a Degradation Delay DD period, DF being a constant having a value which is the desired submodel performance with respect to full performance. The Degradation Delay is instituted, the RTC is sampled from time to time to obtain a test third time T3. When a test T3 minus T2 is not less than DD, then T1 is set to T3. Then, the procedure is repeated for a next group of instructions. Optionally, further accuracy can be achieved by treating “wait-type” and/or “RTC-access-type” instructions specially and also by calculating a DDExtra period value which is used to adjust the next DD.

摘要翻译： 一种简单准确的处理器降额方法包括：对实时计数器/时钟进行采样也获得初始时间值T 1; 复位一个Icnt计数器; 增加Icnt计数器以反映每个指令的处理; 将Icnt计数器中的计数与预定计数IcntMax进行比较，并且如果Icnt计数器中的计数至少为IcntMax，则对RTC进行采样以获得第二时间T 2。 然后从T 2中减去T 1以获得乘以（（1-1 / DF）-1）的时差DT，以获得降级延迟DD周期，DF是具有作为期望子模型性能的值的常数 关于完整的表现。 降级延迟建立，RTC不时采样，以获得第三次T 3的测试。 当测试T 3减去T 2不小于DD时，则T 1被设置为T 3。 然后，针对下一组指令重复该过程。 可选地，可以通过特别地处理“等待类型”和/或“RTC访问型”指令并且还可以通过计算用于调整下一个DD的DDExtra周期值来实现进一步的准确性。

公开(公告)号：US06915405B2

公开(公告)日：2005-07-05

申请号：US10309460

申请日：2002-12-04

申请人： Bruce A. Noyes

发明人： Bruce A. Noyes

IPC分类号： G06F9/455 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F9/45537 ,  G06F12/1027

摘要： A host computer system, including an addressable main memory storing data pages and a page table, emulates a target computer system which includes an emulated target central processing unit, an emulated target associative memory and an emulated target multi-digit incrementable validity counter. The target associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the target processor when access to a given page in main memory is sought. Each entry in the target associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. The target multi-digit counter stores a current validity count. When access to a data page is sought, comparisons are made: 1) between the high order virtual address component of the data page and the high order virtual address component read from the target associative memory entry; and 2) between the multi-digit validity count read from the target associative memory entry and the multi-digit current validity count in the target counter. If there is a full match, the real page address of the requested page is read from the target associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the target associative memory is updated accordingly.

摘要翻译： 包括存储数据页和页表的可寻址主存储器的主计算机系统模拟包括仿真目标中央处理单元，仿真目标关联存储器和仿真目标多位可递增有效性计数器的目标计算机系统。 目标关联存储器在寻求对主存储器中的给定页面的访问时，根据由目标处理器发出的低阶虚拟地址组件来存储多个条目。 目标关联存储器中的每个条目包括分别保存的字段：1）高阶虚拟地址分量; 2）真实页面地址; 和3）多位数有效性计数。 目标多位计数器存储当前的有效性计数。 当寻求对数据页的访问时，进行比较：1）数据页的高阶虚拟地址组件和从目标关联存储器条目读取的高阶虚拟地址组件之间; 和2）从目标关联存储器条目读取的多位数有效性计数与目标计数器中的多位数当前有效性计数之间。 如果存在完全匹配，则从目标关联存储器条目读取所请求页面的真实页面地址。 如果没有匹配，则查询页表以获得所请求页面的真实地址，并相应地更新目标关联存储器。

公开(公告)号：US20050071793A1

公开(公告)日：2005-03-31

申请号：US10675851

申请日：2003-09-30

申请人： David Selway ,  Boubaker Shaiek

发明人： David Selway ,  Boubaker Shaiek

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/505 ,  G06F17/504

摘要： A process for determining the optimum load driving capacity for each driving node in a complex logic circuit is disclosed. First, the logic equations of the logic circuit are extracted from a circuit description. Then, the fan-out of each driving node is analyzed to determine if the total number of pass transistor loads of the analyzed node is excessive compared to a predetermined driving capacity. For each flagged node, logic equations are added which represent the sum of the node's pass transistor loads, and further logic equations are added to compare the number of pass transistors turned on from one to the absolute maximum for the node. Then, a formal proof program is used to analyze the logic circuit and determine which of the comparators have a true output. For each flagged node, the comparator for the largest number which has a possible true output is identified to determine the highest possible actual load for the node; and, if necessary, the driving capacity of the node is adjusted to handle the determined highest possible actual load.

摘要翻译： 公开了一种用于确定复杂逻辑电路中每个驱动节点的最佳负载驱动能力的过程。 首先，从电路描述中提取逻辑电路的逻辑方程。 然后，分析每个驱动节点的扇出，以确定分析节点的传输晶体管负载的总数是否与预定的驱动能力相比过大。 对于每个标记的节点，添加表示节点的传输晶体管负载的总和的逻辑方程，并且添加另外的逻辑方程来比较从一个到该绝对最大值的传输晶体管的数量。 然后，使用形式证明程序来分析逻辑电路，并确定哪些比较器具有真实的输出。 对于每个标记的节点，识别具有可能真实输出的最大数量的比较器，以确定节点的最高可能实际负载; 并且如果需要，调整节点的驾驶能力以处理确定的最高可能的实际负载。

公开(公告)号：US06868483B2

公开(公告)日：2005-03-15

申请号：US10256289

申请日：2002-09-26

申请人： Wayne R. Buzby ,  Charles P. Ryan

发明人： Wayne R. Buzby ,  Charles P. Ryan

IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F9/52 ,  G06F12/0815

摘要： In a multiprocessor data processing system including: a main memory; at least first and second shared caches; a system bus coupling the main memory and the first and second shared caches; at least four processors having respective private caches with the first and second private caches being coupled to the first shared cache and to one another via a first internal bus, and the third and fourth private caches being coupled to the second shared cache and to one another via a second internal bus; method and apparatus for preventing hogging of ownership of a gateword stored in the main memory and which governs access to common code/data shared by processes running in at least three of the processors. Each processor includes a gate control flag. A gateword CLOSE command, establishes ownership of the gateword in one processor and prevents other processors from accessing the code/data guarded until the one processor has completed its use. A gateword OPEN command then broadcasts a gateword interrupt to set the flag in each processor, delays long enough to ensure that the flags have all been set, writes an OPEN value into the gateword and flushes the gateword to main memory. A gateword access command executed by a requesting processor checks its gate control flag, and if set, starts a fixed time delay after which normal execution continues.

摘要翻译： 一种多处理器数据处理系统，包括：主存储器; 至少第一和第二共享高速缓存; 耦合主存储器和第一和第二共享高速缓存的系统总线; 具有相应私有高速缓存的至少四个处理器具有第一和第二专用高速缓存，其经由第一内部总线耦合到第一共享高速缓存并且彼此耦合，并且第三和第四专用高速缓存耦合到第二共享高速缓存并且彼此耦合 通过第二条内部总线; 用于防止存储在主存储器中的门词的所有权陷入的方法和装置，并且其控制对在至少三个处理器中运行的进程共享的公共代码/数据的访问。 每个处理器包括一个门控制标志。 门字关闭命令，确定一个处理器中的门字的所有权，并防止其他处理器访问代码/数据，直到一个处理器完成使用。 门字OPEN命令然后广播门字中断以在每个处理器中设置标志，延迟足够长的时间以确保标志已经被设置，将OPEN值写入门字并将门字刷新到主存储器。 由请求处理器执行的门字访问命令检查其门控制标志，并且如果被设置，则启动固定的时间延迟，之后继续正常执行。

公开(公告)号：US20040111585A1

公开(公告)日：2004-06-10

申请号：US10309459

申请日：2002-12-04

申请人： Bull HN Information Systems Inc.

发明人： Bruce A. Noyes ,  Russell W. Guenthner

IPC分类号： G06F012/00

CPC分类号： G06F12/1027

摘要： A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter. If there is a full match, a switch issues the real page address read from the associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the associative memory is updated accordingly.

摘要翻译： 计算机系统包括中央处理单元，存储数据页和页表的可寻址主存储器和关联存储器。 关联存储器根据当CPU处理器发出的低阶虚拟地址组件访问主存储器中的给定页面时存储多个条目。 关联存储器中的每个条目包括分别保持：1）高阶虚拟地址分量的字段; 2）真实页面地址; 和3）多位数有效性计数。 CPU中可增量的多位计数器存储当前的有效性计数。 当寻求访问数据页时，比较器接收：1）数据页的高阶虚拟地址分量; 2）从关联存储器条目读取的高阶虚拟地址组件; 3）从关联存储器条目读取的多位数有效性计数; 和4）计数器中的多位数的当前有效性计数。 如果完全匹配，则交换机会发出从关联内存条目读取的真实页面地址。 如果没有匹配，则查询页表以获得所请求页面的真实地址，并且相关联的存储器被相应地更新。

公开(公告)号：US20030140041A1

公开(公告)日：2003-07-24

申请号：US09896702

申请日：2001-06-29

申请人： Bull HN Information Systems Inc

发明人： Kenneth R. Rosensteel JR. ,  Ken Allen ,  William Lawrance

IPC分类号： G06F007/00

CPC分类号： G06F9/544 ,  G06F3/0601 ,  G06F2003/0697 ,  Y10S707/99942

摘要： Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.

公开(公告)号：US20030131109A1

公开(公告)日：2003-07-10

申请号：US09896156

申请日：2001-06-29

申请人： Bull HN Information Systems Inc.

发明人： Kenneth R. Rosensteel JR. ,  William Lawrance ,  Howard Hagan

IPC分类号： G06F015/167 ,  G06F015/16

CPC分类号： G06F9/45537 ,  Y10S707/99953

摘要： Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.

摘要翻译： 批量数据由第一计算机系统上的应用程序读取或写入第二异构计算机系统上的文件。 或者，它在这些异构系​​统上的应用程序之间直接读取或写入批量数据。 作业或任务从一个系统启动到在第二个异构系统上执行。 然后将结果返回到第一个系统。 还从第一个系统启动检查点和以后重新启动，以在第二个异构系统上执行。