发明授权
US5675168A Unsymmetrical MOS device having a gate insulator area offset from the
source and drain areas, and ESD protection circuit including such a MOS
device
失效
具有偏离源极和漏极区域的栅极绝缘体区域的非对称MOS器件，以及包括这种MOS器件的ESD保护电路
- 专利标题： Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device
- 专利标题（中）： 具有偏离源极和漏极区域的栅极绝缘体区域的非对称MOS器件，以及包括这种MOS器件的ESD保护电路
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申请号： US415928申请日： 1995-04-03
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公开(公告)号： US5675168A公开(公告)日： 1997-10-07
- 发明人: Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
- 申请人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
- 申请人地址： JPX Osaka
- 专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址： JPX Osaka
- 优先权： JPX6-064973 19940401
- 主分类号： H01L27/02
- IPC分类号： H01L27/02 ; H01L27/088 ; H01L29/08 ; H01L29/78 ; H01L23/60
摘要：
An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.
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