发明授权
US5677208A Method for making FET having reduced oxidation inductive stacking fault
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制造具有减少的氧化感应堆垛层错的FET的方法
- 专利标题： Method for making FET having reduced oxidation inductive stacking fault
- 专利标题（中）： 制造具有减少的氧化感应堆垛层错的FET的方法
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申请号： US410373申请日： 1995-03-24
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公开(公告)号： US5677208A公开(公告)日： 1997-10-14
- 发明人: Hiroyasu Itou , Hideya Inagaki
- 申请人： Hiroyasu Itou , Hideya Inagaki
- 申请人地址： JPX Kariya
- 专利权人： Nippondenso Co., Ltd.
- 当前专利权人： Nippondenso Co., Ltd.
- 当前专利权人地址： JPX Kariya
- 优先权： JPX6-055783 19940325
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/225 ; H01L21/265 ; H01L21/322 ; H01L21/336 ; H01L21/8234 ; H01L23/544
摘要：
An improved manufacturing method for a semiconductor device, which can reduce process inductive fault such as oxidation inductive stacking fault (OSF) and contribute to the improvement of the electric characteristics of the semiconductor device, is disclosed. A thermal oxide film is formed on a semiconductor substrate, then a nitride film is formed and a medium temperature heat treatment is provided to the semiconductor substrate within a temperature range from 600.degree. C. to 1,000.degree. C., whereby an interstitial oxygen concentration can be lowered. Subsequently, ion implantation, etc. are provided as a well region forming process, and a drive-in process is performed by means of a high temperature heat treatment. At this time, ion implantation dose is set to 9.times.10.sup.13 �cm.sup.-2 ! or less, and the temperature of the heat treatment is lowered or the duration of the teat treatment is shortened. After this, an element separation layer process is performed, and a gate oxide film, a gate electrode, a source/drain layer, a CVD oxide film, a contact hole and a metal wire are formed.
公开/授权文献
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