A process has been developed in which a deep submicron MOSFET device has been fabricated, featuring a local, narrow threshold voltage adjust region, in a semiconductor substrate, with the narrow threshold voltage adjust region, self aligned to an overlying, narrow, polycide gate structure. The process consists of forming a narrow hole opening in an insulator layer, where the insulator layer overlies a polysilicon layer and a gate insulator layer. An ion implantation procedure, through the polysilicon layer, and gate insulator layer, is used to place a narrow threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. Deposition of a metal layer, followed by an anneal procedure, converts the top portion of polysilicon, in the narrow hole opening, to a metal silicide structure. After removal of unreacted metal, and insulator layer, the polysilicon layer is patterned, via RIE procedures, using the metal silicide structure as a mask, to create a narrow polycide gate structure, comprised of an overlying, narrow metal silicide gate, and an underlying, narrow polysilicon gate structure. The narrow polycide gate structure is self aligned to the underlying, narrow threshold voltage adjust region.