发明授权
- 专利标题: Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
- 专利标题(中): 减少脉冲填充同步数字通信中等待时间抖动的方法和装置
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申请号: US429951申请日: 1995-04-27
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公开(公告)号: US5680422A公开(公告)日: 1997-10-21
- 发明人: Richard A. Burch , Kevin W. Schneider , Michael D. Turner , Timothy D. Rochell
- 申请人: Richard A. Burch , Kevin W. Schneider , Michael D. Turner , Timothy D. Rochell
- 申请人地址: AL Huntsville
- 专利权人: Adtran
- 当前专利权人: Adtran
- 当前专利权人地址: AL Huntsville
- 主分类号: H04J3/07
- IPC分类号: H04J3/07 ; H04L7/00
摘要:
A wander reduction mechanism in an HDSL pulse-stuffing synchronization system provides a more precise measure of the phase of the incoming asynchronous signal than is obtained in conventional schemes, in which the only information available is the presence or absence of stuffing pulses. An auxiliary phase comparator and phase adjuster are incorporated into the synchronizer-multiplexer to generate a reference data clock (derived from the synchronized data clock), so that the incoming unsynchronized data clock can be tracked. As the clock is iteratively phase-adjusted, the respective changes are accumulated. At the end of a prescribed measurement interval, the net contents of the accumulator are encoded and transported over the synchronous digital data communication channel to the receiver. By decoding this sequence information, the desynchronizer is able to generate a desynchronized data clock having the same number of net phase adjustments during a measurement period as the reference clock at the synchronizer.
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