-
1.发明授权Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications 失效减少脉冲填充同步数字通信中等待时间抖动的方法和装置
公开(公告)号：US5680422A
公开(公告)日：1997-10-21
申请号：US429951
申请日：1995-04-27
CPC分类号： H04J3/073
摘要： A wander reduction mechanism in an HDSL pulse-stuffing synchronization system provides a more precise measure of the phase of the incoming asynchronous signal than is obtained in conventional schemes, in which the only information available is the presence or absence of stuffing pulses. An auxiliary phase comparator and phase adjuster are incorporated into the synchronizer-multiplexer to generate a reference data clock (derived from the synchronized data clock), so that the incoming unsynchronized data clock can be tracked. As the clock is iteratively phase-adjusted, the respective changes are accumulated. At the end of a prescribed measurement interval, the net contents of the accumulator are encoded and transported over the synchronous digital data communication channel to the receiver. By decoding this sequence information, the desynchronizer is able to generate a desynchronized data clock having the same number of net phase adjustments during a measurement period as the reference clock at the synchronizer.
摘要翻译： 在HDSL脉冲填充同步系统中的漫游减少机制提供了比传统方案中获得的输入异步信号的相位更精确的测量，其中唯一可用的信息是填充脉冲的存在或不存在。 辅助相位比较器和相位调节器被并入到同步器多路复用器中以产生参考数据时钟（从同步数据时钟导出），使得可以跟踪输入的不同步的数据时钟。 随着时钟被迭代地相位调整，各个变化被累积。 在规定的测量间隔结束时，累加器的净内容被编码并通过同步数字数据通信信道传送到接收机。 通过对该序列信息进行解码，去同步器能够在测量周期期间产生具有相同数量的净相位调整的去同步数据时钟作为同步器处的参考时钟。
-
公开(公告)号：US06608840B2
公开(公告)日：2003-08-19
申请号：US10131654
申请日：2002-04-24
IPC分类号： H04J316
CPC分类号： H04L25/4917 , H04L25/03343 , H04L25/497 , H04L25/4975 , H04Q11/0435 , H04Q11/0471 , H04Q2213/1303 , H04Q2213/13034 , H04Q2213/13094 , H04Q2213/1319 , H04Q2213/13199 , H04Q2213/13209 , H04Q2213/13216 , H04Q2213/13322
摘要： The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.
-
公开(公告)号：US5999542A
公开(公告)日：1999-12-07
申请号：US133061
申请日：1998-08-12
IPC分类号： H04L25/03 , H04L25/49 , H04L25/497 , H04Q11/04 , H04J1/00
CPC分类号： H04L25/4917 , H04L25/03343 , H04L25/497 , H04L25/4975 , H04Q11/0435 , H04Q11/0471 , H04Q2213/1303 , H04Q2213/13034 , H04Q2213/13094 , H04Q2213/1319 , H04Q2213/13199 , H04Q2213/13209 , H04Q2213/13216 , H04Q2213/13322
摘要： The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.
-
公开(公告)号：US5809033A
公开(公告)日：1998-09-15
申请号：US560812
申请日：1995-11-20
IPC分类号： H04L25/03 , H04L25/49 , H04L25/497 , H04Q11/04 , H04J3/12
CPC分类号： H04L25/4917 , H04L25/03343 , H04L25/497 , H04L25/4975 , H04Q11/0435 , H04Q11/0471 , H04Q2213/1303 , H04Q2213/13034 , H04Q2213/13094 , H04Q2213/1319 , H04Q2213/13199 , H04Q2213/13209 , H04Q2213/13216 , H04Q2213/13322
摘要： The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.
-
5.发明授权Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications 失效减少脉冲填充同步数字通信中等待时间抖动的方法和装置
公开(公告)号：US5619506A
公开(公告)日：1997-04-08
申请号：US429950
申请日：1995-04-27
IPC分类号： H04J3/07
CPC分类号： H04J3/073
摘要： A jitter/wander reduction mechanism monitors the ratio of pulse stuffing, to detect whenever the pulse stuffing ratio is proximate a prescribed undesirable ratio of stuffs per stuffing opportunity, which causes the wander to be a large number of unit intervals. A stuffing pulse accumulator-controlled frequency shift control circuit monitors the signal produced by a multiplexer (and demultiplexer for full duplex mode) control logic circuit and incrementally adjusts, as necessary, the frequency of a synchronized clock signal input to the multiplexer (and demultiplexer). The magnitude of the incremental frequency shift is sufficient to drive the synchronized clock away from the frequency associated with the undesired stuff ratio to a frequency that is sufficiently separated from the undesired value to produce a stuffing ratio other than the undesired value and reduce the jitter/wander.
摘要翻译： 抖动/漂移减少机制监测脉冲填充的比率，以便每当脉冲填充比接近于每个填充机会的填充物的规定的不期望比例时检测，这导致漂移是大量的单位间隔。 填充脉冲累加器控制的频移控制电路监视由多路复用器（和全双工模式的解复用器）控制逻辑电路产生的信号，并根据需要递增地调整输入到多路复用器（和解复用器）的同步时钟信号的频率， 。 增量频移的大小足以将同步时钟从与不需要的填充比相关联的频率驱动到与不期望值充分分离的频率，以产生除了不需要的值之外的填充比，并减少抖动/ 漫步。
-
公开(公告)号：US5526377A
公开(公告)日：1996-06-11
申请号：US354366
申请日：1994-12-12
CPC分类号： H04B3/23
摘要： The need to employ costly precision components to reduce non-linearities in the signal processing path of noise reduction circuitry such as an echo canceler and decision feedback equalizer is successfully addressed by a transversal filter which is capable of effectively tracking for non-linearities in system components that manifest themselves as added noise introduced into the signal propagation path. This non-linear tracking capability is attained by employing cascaded sets of weighting coefficient and scaling factor multiplying stages. The first set of weighting coefficients effectively modifies the contents of each of the transmitted symbol samples in the transversal filter delay line to produce respective sets of `partial sums` associated with the respective data symbols employed in the data modulation scheme. The second, cascaded set of `scaling` coefficients or factors is employed to scale selected ones of the sets of the partial sums.
-
7.发明授权Transversal filter useable in echo canceler, decision feedback equalizer applications for minimizing non-linear distortion in signals conveyed over full duplex two-wire communication link 失效用于回波消除器的横向滤波器，决策反馈均衡器应用，用于最小化通过全双工双线通信链路传送的信号中的非线性失真
公开(公告)号：US5396517A
公开(公告)日：1995-03-07
申请号：US26491
申请日：1993-03-04
CPC分类号： H04B3/23
摘要： The need to employ costly precision components to reduce non-linearities in the signal processing path of noise reduction circuitry such as an echo canceler and decision feedback equalizer is successfully addressed by a transversal filter which is capable of effectively tracking for non-linearities in system components that manifest themselves as added noise introduced into the signal propagation path. This non-linear tracking capability is attained by employing cascaded sets of weighting coefficient and scaling factor multiplying stages. The first set of weighting coefficients effectively modifies the contents of each of the transmitted symbol samples in the transversal filter delay line to produce respective sets of `partial sums` associated with the respective data symbols employed in the data modulation scheme. The second, cascaded set of `scaling` coefficients or factors is employed to scale selected ones of the sets of the partial sums.
摘要翻译： 需要采用昂贵的精密元件来减少诸如回波消除器和判决反馈均衡器之类的噪声降低电路的信号处理路径中的非线性，这是通过横向滤波器来解决的，该滤波器能够有效跟踪系统组件中的非线性 这表现为引入信号传播路径的附加噪声。 这种非线性跟踪能力通过采用级联的加权系数和比例因子乘法级来实现。 第一组加权系数有效地修改横向滤波器延迟线中每个发射符号样本的内容，以产生与在数据调制方案中采用的相应数据符号相关联的各个“部分和”集合。 使用第二级联的“缩放”系数或因子来缩放部分和的集合中的所选择的一组。
-
8.发明授权Use of modified line encoding and low signal-to-noise auto ratio based signal processing to extend range of digital data transmission over repeaterless two-wire telephone link 有权使用经修改的线路编码和基于信噪比的低信号处理可以通过无中继的两线电话链路扩展数字数据传输的范围公开(公告)号：US06393029B1
公开(公告)日：2002-05-21
申请号：US09438555
申请日：1999-11-10
IPC分类号： H04L1228
CPC分类号： H04L25/4917 , H04L25/03343 , H04L25/497 , H04L25/4975 , H04Q11/0435 , H04Q11/0471 , H04Q2213/1303 , H04Q2213/13034 , H04Q2213/13094 , H04Q2213/1319 , H04Q2213/13199 , H04Q2213/13209 , H04Q2213/13216 , H04Q2213/13322
摘要： The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.
摘要翻译： 可以通过从两个信息比特来增加ISDN线路码的容量来扩展数字数据通信服务的范围，例如基本速率2B1Q ISDN信道到位于超出行业标准可实现的两线环路范围的客户驻地 符号到每个符号三个信息位，以便减少有效符号率，其被纠错编码为有效的4B1H线路码，用于定义十六电平PAM信号波形，并采用增强的低信噪比信号处理技术 在发射机和接收机中，以适应由于其延长的长度而导致的双线线路的增加的插入损耗。 这种增强的低信噪比信号处理技术包括发射机中的Tomlinson预编码器，以及接收机中的自适应线性均衡器和模块单元。
-
9.发明授权Jitter/wander reduction circuit for pulse-stuffed, synchronized digital communications 失效用于脉冲填充，同步数字通信的抖动/漫游减少电路
公开(公告)号：US5539785A
公开(公告)日：1996-07-23
申请号：US281461
申请日：1994-07-27
CPC分类号： H04J3/073
摘要： A jitter/wander reduction circuit is provided for a desynchronizer deriving an output clock signal from an independent clock signal and phase adjustment signals. Phase adjustment signals relate to a deviation of the independent clock signal from an input clock signal. The circuit includes a frequency offset estimation circuit receiving phase adjustment signals and providing a frequency offset estimation signal. A phase controller receives the frequency offset estimation signal, provides a feedback signal to the frequency offset estimation circuit, and provides a phase difference signal. A clock generator circuit receives the independent clock signal and the phase difference signal. The independent clock signal is adjusted based on the phase difference signal to provide an output clock signal.
摘要翻译： 提供抖动/漂移减少电路用于从独立时钟信号和相位调整信号导出输出时钟信号的去同步器。 相位调整信号与独立时钟信号与输入时钟信号的偏差有关。 电路包括频率偏移估计电路，其接收相位调整信号并提供频率偏移估计信号。 相位控制器接收频偏估计信号，向频偏估计电路提供反馈信号，并提供相位差信号。 时钟发生器电路接收独立时钟信号和相位差信号。 基于相位差信号调整独立时钟信号以提供输出时钟信号。
-
10.发明授权Digital phase locked loop having adaptive bandwidth for pulse stuffing synchronized digital communication system 失效数字锁相环具有脉冲填充同步数字通信系统的自适应带宽
公开(公告)号：US5793824A
公开(公告)日：1998-08-11
申请号：US641226
申请日：1996-04-30
CPC分类号： H03L7/093 , H03L7/091 , H03L7/0993 , H04J3/076
摘要： A bandwidth-adaptive digital phase locked loop-based clock control arrangement controls the generation of a read-out clock used for retiming digital data signal interfaced with a synchronous data channel of a communication system, in which pulse-stuffing synchronization is employed to maintain clock synchronization of the digital data signal that is not bit-synchronous with a synchronous digital data channel over which the digital data signal is transported. The bandwidth-adaptive digital phase locked loop includes a loop filter to which the error signal is applied and a phase accumulator, coupled to the output of the loop filter and being operative to stepwise adjust the read-out clock signal. The loop filter has a first scaled path that includes a first, controllably stepped gain stage, and a second scaled path that includes a second, controllably stepped gain stage coupled to a frequency accumulator. The output of the frequency accumulator and the first stepped gain stage are summed and coupled to the phase accumulator. The gain of each of the first and second gain stages is incrementally adjusted in accordance with the magnitude of the error signal.
摘要翻译： 带宽自适应数字锁相环的时钟控制装置控制用于重新定时与通信系统的同步数据信道接口的数字数据信号的读出时钟的产生，其中使用脉冲填充同步来维持时钟 与传送数字数据信号的同步数字数据信道不同步的数字数据信号的同步。 带宽自适应数字锁相环包括施加误差信号的环路滤波器和耦合到环路滤波器的输出并且可操作以逐步调节读出时钟信号的相位累加器。 环路滤波器具有包括第一可控阶梯增益级的第一缩放路径和包括耦合到频率累加器的第二可控阶梯增益级的第二缩放路径。 频率累加器和第一阶梯增益级的输出被相加并耦合到相位累加器。 第一增益级和第二增益级中的每一个的增益根据误差信号的幅度进行递增调整。
-
-
-
-
-
-
-
-
-
搜索结果
77 条记录 (耗时 0.027 秒)
