发明授权
US5689465A Semiconductor memory device and defective memory cell correction circuit
失效
半导体存储器件和缺陷存储单元校正电路
- 专利标题： Semiconductor memory device and defective memory cell correction circuit
- 专利标题（中）： 半导体存储器件和缺陷存储单元校正电路
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申请号： US703178申请日： 1996-08-26
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公开(公告)号： US5689465A公开(公告)日： 1997-11-18
- 发明人: Shunichi Sukegawa , Takumi Nasu , Hidetoshi Iwai
- 申请人： Shunichi Sukegawa , Takumi Nasu , Hidetoshi Iwai
- 申请人地址： TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： TX Dallas
- 优先权： JPX4-185926 19920619
- 主分类号： G11C29/00
- IPC分类号： G11C29/00 ; G11C7/00
摘要：
To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.
公开/授权文献
- US5150123A Field disturbance monitor system 公开/授权日：1992-09-22
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