发明授权
- 专利标题: Method for designing a large scale integrated (LSI) layout
- 专利标题(中): 大规模集成(LSI)布局设计方法
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申请号: US631904申请日: 1996-04-12
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公开(公告)号: US5694328A公开(公告)日: 1997-12-02
- 发明人: Emi Hayashi , Hiroyuki Miyamoto , Yoshihiro Tabira
- 申请人: Emi Hayashi , Hiroyuki Miyamoto , Yoshihiro Tabira
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electronics Corporation
- 当前专利权人: Matsushita Electronics Corporation
- 当前专利权人地址: JPX Osaka
- 优先权: JPX4-210028 19920806
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; H01L27/02
摘要:
A plurality of cells which have input terminals and output terminals on four sides are divided into a plurality of groups of cells. The plurality of cells are placed in an array form at positions which are either adjacent or nonadjacent. A plurality of groups of cells are placed one after another such that the resulting layout becomes substantially rectangular or square. Power buses are routed parallel to each other, and power supply lines are routed from the power buses to cells. Data lines are routed between the terminals of the cells.