发明授权
- 专利标题: Error correction method including erasure correction, and apparatus therefor
- 专利标题(中): 包括擦除校正的纠错方法及其装置
-
申请号: US230249申请日: 1994-04-20
-
公开(公告)号: US5694330A公开(公告)日: 1997-12-02
- 发明人: Keiichi Iwamura , Takayuki Aizawa , Izumi Narita , Takatoshi Suzuki
- 申请人: Keiichi Iwamura , Takayuki Aizawa , Izumi Narita , Takatoshi Suzuki
- 申请人地址: JPX Tokyo
- 专利权人: Canon Kabushiki Kaisha
- 当前专利权人: Canon Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX5-094408 19930421
- 主分类号: G06F11/10
- IPC分类号: G06F11/10 ; H03M13/00 ; H03M13/15
摘要:
A multiplier calculates a product S'(x)=S(x).multidot..lambda.(x) mod X.sup.d-1 of a syndrome polynomial S(x) generated by a syndrome generator and an erasure position polynomial .lambda.(x) generated by an erasure position polynomial generator, modulo X.sup.d-1. A constant multiplier sequentially multiplies coefficients of the polynomial S'(x) and the erasure position polynomial .lambda.(x) with a power of a primitive root .alpha. of a code. The power exponents in this multiplication are determined in units of coefficients. Every time this multiplication is executed, an adder sequentially adds predetermined combinations of products. A plurality of arithmetic and logic operations according to the numbers of correctable erasures and errors are sequentially executed using the sums. A divisor and dividend are selected in accordance with the number of erasures included in the code on the basis of the plurality of arithmetic and logic operation results. A division is executed using the selected divisor and dividend. A value at a position, discriminated to be an error position, of the code is corrected based on the division result, thus performing error correction including erasure correction with a simple circuit arrangement.
公开/授权文献
- US6142029A Axoid force mechanism 公开/授权日:2000-11-07