发明授权
- 专利标题: Input protection circuit and method of fabricating semiconductor integrated circuit
- 专利标题(中): 输入保护电路及制造半导体集成电路的方法
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申请号: US638766申请日: 1996-04-29
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公开(公告)号: US5696397A公开(公告)日: 1997-12-09
- 发明人: Isami Sakai
- 申请人: Isami Sakai
- 申请人地址: JPX Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX7-106391 19950428
- 主分类号: H01L29/78
- IPC分类号: H01L29/78 ; H01L21/336 ; H01L21/8238 ; H01L27/02 ; H01L27/06 ; H01L27/092 ; H01L23/62
摘要:
The present invention provides an input protection circuit including a first MOS FET including a source electrically connected to an input terminal and a drain and a gate both electrically connected to a grounding line, a second MOS FET including a source electrically connected to the input terminal and a drain and a gate, and a third MOS FET including a source electrically connected to a power line and a drain and a gate to both of which are electrically connected a drain and a gate of the second MOS FET. The input protection circuit shares a parasitic p-MOS transistor with an internal circuit, and hence it is no longer necessary to form a parasitic MOS transistor to be used only for an input protection circuit. Thus, the input protection circuit decreases the number of photomask using steps by one relative to a conventional protection circuit. In addition, the sharing a parasitic MOS transistor with an internal circuit makes it possible to prevent a current from running from an input terminal to a power line, even if a voltage higher than a source voltage is input to the input terminal. Thus, it is possible to enhance resistance to electrostatic breakdown, and fabricate an integrated circuit having high reliability with lower cost.
公开/授权文献
- US5151837A Composite magnetic head 公开/授权日:1992-09-29
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