公开(公告)号：US08035155B2

公开(公告)日：2011-10-11

申请号：US12320965

申请日：2009-02-10

申请人： Isami Sakai

发明人： Isami Sakai

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device includes a floating gate; an erasing gat; and a control gate. The floating gate is provided on a channel region of a semiconductor substrate through a first insulating layer. The erasing gate is provided on the floating gate through a second insulating layer. The control gate is provided beside the floating gate and the erasing gate through a third insulating layer. The floating gate is U-shaped.

摘要翻译： 非易失性半导体存储器件包括浮置栅极; 擦掉盖子 和控制门。 浮置栅极通过第一绝缘层设置在半导体衬底的沟道区上。 擦除栅极通过第二绝缘层设置在浮栅上。 控制栅极通过第三绝缘层设置在浮置栅极和擦除栅极旁边。 浮动门是U形的。

公开(公告)号：US06287907B1

公开(公告)日：2001-09-11

申请号：US09447869

申请日：1999-11-23

申请人： Hiroshi Ito ,  Isami Sakai

发明人： Hiroshi Ito ,  Isami Sakai

IPC分类号： H01L218238

CPC分类号： H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11543

摘要： According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, a gate electrode of a select-transistor is composed of a single layer of a polysilicon film, which is formed from the same layer as the floating gate electrode of the memory-transistor and then doped to have an enhanced dopant concentration by ion implantation performed in the step of forming source-drain regions of the transistors

摘要翻译： 根据本发明，公开了一种2晶体管型闪速存储器，其中存储晶体管由由浮置栅极和由第一绝缘膜隔开的控制栅极组成的结构层组成; 并且至少选择晶体管的栅电极由与存储晶体管的浮置栅电极相同的层形成的单层多晶硅膜构成，然后掺杂以具有增强的掺杂浓度 通过在形成晶体管的源极 - 漏极区域的步骤中执行的离子注入

公开(公告)号：US5696397A

公开(公告)日：1997-12-09

申请号：US638766

申请日：1996-04-29

申请人： Isami Sakai

发明人： Isami Sakai

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L23/62

CPC分类号： H01L27/0266 ,  H01L2924/0002

摘要： The present invention provides an input protection circuit including a first MOS FET including a source electrically connected to an input terminal and a drain and a gate both electrically connected to a grounding line, a second MOS FET including a source electrically connected to the input terminal and a drain and a gate, and a third MOS FET including a source electrically connected to a power line and a drain and a gate to both of which are electrically connected a drain and a gate of the second MOS FET. The input protection circuit shares a parasitic p-MOS transistor with an internal circuit, and hence it is no longer necessary to form a parasitic MOS transistor to be used only for an input protection circuit. Thus, the input protection circuit decreases the number of photomask using steps by one relative to a conventional protection circuit. In addition, the sharing a parasitic MOS transistor with an internal circuit makes it possible to prevent a current from running from an input terminal to a power line, even if a voltage higher than a source voltage is input to the input terminal. Thus, it is possible to enhance resistance to electrostatic breakdown, and fabricate an integrated circuit having high reliability with lower cost.

摘要翻译： 本发明提供了一种输入保护电路，包括：第一MOS FET，其包括电连接到输入端子的源极，漏极和电连接到接地线的栅极;第二MOS FET，其包括电连接到输入端子的源极;以及 漏极和栅极，以及包括电连接到电力线，漏极和栅极的源极的第三MOS FET，二者都与第二MOS FET的漏极和栅极电连接。 输入保护电路共享具有内部电路的寄生p-MOS晶体管，因此不再需要形成仅用于输入保护电路的寄生MOS晶体管。 因此，输入保护电路相对于传统的保护电路使用步骤1减少光掩模的数量。 此外，即使将高于源电压的电压输入到输入端子，共享具有内部电路的寄生MOS晶体管也可以防止电流从输入端子运行到电力线。 因此，可以提高抗静电击穿性，并且以较低的成本制造具有高可靠性的集成电路。

公开(公告)号：US5565383A

公开(公告)日：1996-10-15

申请号：US586422

申请日：1996-01-16

申请人： Isami Sakai

发明人： Isami Sakai

IPC分类号： H01L21/285 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659

摘要： In a method for forming silicide films on a silicon substrate being formed thereon with a gate surrounded by gate side walls and being formed therein with diffusion regions, the silicide film being formed on a predetermined region of the silicon substrate at least except for an extremely thin film on the gate side walls. The method comprises the following steps. The silicon substrate is subjected to a collimated sputtering of metal atoms with use of a meshed mask on the silicon substrate surface to deposit a metal film on an entire surface of the silicon substrate, except for an extremely thin film on the vertical walls. The deposited metal film is further subjected to a heat treatment to react the metal film with the diffusion regions to thereby selectively form a metal silicide film at least on the diffusion regions, except for an extremely thin film on the vertical walls.

摘要翻译： 在形成有硅栅极上的硅化物膜的方法中，栅极由栅极侧壁围绕并形成有扩散区，硅化物膜至少形成在硅衬底的预定区域上， 电影在门侧墙上。 该方法包括以下步骤。 硅衬底在硅衬底表面上使用网状掩模进行金属原子的准直溅射，以在垂直壁上的极薄膜之外在硅衬底的整个表面上沉积金属膜。 沉积的金属膜进一步进行热处理以使金属膜与扩散区反应，至少在扩散区域上选择性地形成金属硅化物膜，除了垂直壁上的极薄膜。

公开(公告)号：US5296742A

公开(公告)日：1994-03-22

申请号：US795731

申请日：1991-11-21

申请人： Isami Sakai

发明人： Isami Sakai

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L2924/0002

摘要： An integrated circuit chip includes a substrate in which active circuits are formed, a lower layer of parallel conductors formed on the substrate, and one or more intermediate layers of insulating material on the lower-layer conductors, the intermediate layers having troughs corresponding to spaces where the lower-layer conductors are absent on the substrate and crests corresponding to spaces where the lower-layer conductors are present on the substrate. An upper layer of parallel conductors is formed on the insulative layers, the upper-layer conductors extending in a direction normal to the length of the lower-layer conductors. The upper-layer conductors have a minimum step coverage of 50%, and the lower-layer conductors have a ratio of a thickness thereof to a separation therebetween, which ratio is either equal to or greater than 0.45 or equal to or smaller than 0.25.

摘要翻译： 集成电路芯片包括其中形成有源电路的基板，形成在基板上的平行导体的下层，以及在下层导体上的一个或多个绝缘材料中间层，中间层具有对应于空间的槽 底层上不存在下层导体，对应于衬底上存在下层导体的空间的波峰。 在绝缘层上形成上层平行导体，上层导体沿垂直于下层导体长度的方向延伸。 上层导体的最小阶梯覆盖率为50％，下层导体的厚度与其间的间隔的比率为0.45以上，0.25以上。

公开(公告)号：US5292674A

公开(公告)日：1994-03-08

申请号：US800170

申请日：1991-11-29

申请人： Kazuhiro Okabe ,  Isami Sakai

发明人： Kazuhiro Okabe ,  Isami Sakai

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/6659 ,  H01L29/78

摘要： Disclosed is an improved metal oxide-semiconductor field-effect transistor having two diffused regions extending apart from under one and the other edge of the gate in the opposite directions, at least one of the diffused regions being composed of a first leastdoped, short section, a second lightly-doped, short section, and a third heavily-doped, long section. Either diffused region may be used as drain. The series-connection of least and lightly-doped sections of the same longitudinal size or depth improves the current driving capability of the semiconductor device. Also, methods of making such MOSFETs are disclosed.

摘要翻译： 公开了一种改进的金属氧化物半导体场效应晶体管，其具有在相反方向上从栅极的一个和另一个边缘分开延伸的两个扩散区域，至少一个扩散区域由第一最小二极管，短截面， 第二个轻掺杂的短截面和第三个重掺杂的长截面。 扩散区域可以用作漏极。 具有相同纵向尺寸或深度的最小和轻掺杂部分的串联连接提高了半导体器件的电流驱动能力。 此外，公开了制造这种MOSFET的方法。

公开(公告)号：US5834368A

公开(公告)日：1998-11-10

申请号：US814601

申请日：1997-03-10

申请人： Hiroshi Kawaguchi ,  Isami Sakai

发明人： Hiroshi Kawaguchi ,  Isami Sakai

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/44

CPC分类号： H01L29/66575 ,  H01L21/28518 ,  H01L29/665 ,  Y10S148/147

摘要： A method for manufacturing an integrated circuit, wherein, before providing an IC composite by forming a metal film on an IC assembly which includes a semiconductor substrate and a silicon part formed along the substrate and consisting essentially of silicon, an amorphous region is formed into the silicon part. The IC composite is subjected to first primary and secondary heat treatments in a nitrogen atmosphere and then to a second heat treatment at 600.degree.-700.degree. C., 700.degree.-900.degree. C., and 700.degree.-900.degree. C. to turn the metal film on the silicon part into a metal silicide film of excellent uniformity. The assembly has a silicon dioxide portion, on which the metal film is turned during the first primary and secondary heat treatments into a metal nitride film. The second heat treatment is carried out after the removal of the metal nitride film.

摘要翻译： 一种集成电路的制造方法，其中，在通过在包括半导体衬底和沿着衬底形成并且基本上由硅组成的硅部件的IC组件上形成金属膜来提供IC复合体之前，形成非晶区域 硅部分。 将IC复合体在氮气气氛中进行一次和二次热处理，然后在600-700℃，700-900℃和700-900℃下进行第二次热处理以转动 硅部分上的金属膜变成金属硅化物膜，具有优异的均匀性。 该组件具有二氧化硅部分，金属膜在第一次和二次热处理期间转动到金属氮化物膜中。 在除去金属氮化物膜之后进行第二次热处理。

公开(公告)号：US20090200597A1

公开(公告)日：2009-08-13

申请号：US12320965

申请日：2009-02-10

申请人： Isami Sakai

发明人： Isami Sakai

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device includes a floating gate; an erasing gat; and a control gate. The floating gate is provided on a channel region of a semiconductor substrate through a first insulating layer. The erasing gate is provided on the floating gate through a second insulating layer. The control gate is provided beside the floating gate and the erasing gate through a third insulating layer. The floating gate is U-shaped.

摘要翻译： 非易失性半导体存储器件包括浮置栅极; 擦掉盖子 和控制门。 浮置栅极通过第一绝缘层设置在半导体衬底的沟道区上。 擦除栅极通过第二绝缘层设置在浮栅上。 控制栅极通过第三绝缘层设置在浮置栅极和擦除栅极旁边。 浮动门是U形的。

公开(公告)号：US06979856B2

公开(公告)日：2005-12-27

申请号：US10648295

申请日：2003-08-27

申请人： Teiichiro Nishizaka ,  Isami Sakai ,  Akira Yoshino ,  Shinichi Kawai ,  Kiyokazu Ishige ,  Tomohiro Hamajima ,  Motoko Tanaka

发明人： Teiichiro Nishizaka ,  Isami Sakai ,  Akira Yoshino ,  Shinichi Kawai ,  Kiyokazu Ishige ,  Tomohiro Hamajima ,  Motoko Tanaka

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11568 ,  G11C16/0416 ,  H01L27/115

摘要： A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film. The first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines. The second diffusion region is connected to a program and erase bit line.

摘要翻译： 半导体存储器件包括设置在第一和第二扩散区域之间的半导体衬底上的第一绝缘膜，设置在第一绝缘膜上的第一栅电极，设置在第二扩散区和第三扩散区之间的半导体衬底上的第二绝缘膜 以及设置在第二绝缘膜上的第二栅电极。 第一和第二扩散区域，第一绝缘膜和第一栅电极构成第一存储单元，而第二和第三扩散区域，第二绝缘膜和第二栅电极构成第二存储单元。 第一和第二栅电极共同连接形成字线电极。 第一和第三扩散区域连接到第一和第二读取位线。 第二扩散区连接到编程和擦除位线。

公开(公告)号：US06534355B2

公开(公告)日：2003-03-18

申请号：US09950870

申请日：2001-09-12

申请人： Hiroshi Ito ,  Isami Sakai

发明人： Hiroshi Ito ,  Isami Sakai

IPC分类号： H01L218238

CPC分类号： H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11543

摘要： According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, a gate electrode of a select-transistor is composed of a single layer of a polysilicon film, which is formed from the same layer as the floating gate electrode of the memory-transistor and then doped to have an enhanced dopant concentration by ion implantation performed in the step of forming source-drain regions of the transistors.

摘要翻译： 根据本发明，公开了一种2晶体管型闪速存储器，其中存储晶体管由由浮置栅极和由第一绝缘膜隔开的控制栅极组成的结构层组成; 并且至少选择晶体管的栅电极由与存储晶体管的浮置栅电极相同的层形成的单层多晶硅膜构成，然后掺杂以具有增强的掺杂浓度 通过在形成晶体管的源极 - 漏极区域的步骤中执行的离子注入。