发明授权
- 专利标题: Process for fabricating a semiconductor integrated circuit device
- 专利标题(中): 半导体集成电路器件的制造方法
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申请号: US458615申请日: 1995-06-02
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公开(公告)号: US5700704A公开(公告)日: 1997-12-23
- 发明人: Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
- 申请人: Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX2-30451 19900209; JPX2-30452 19900209; JPX2-30453 19900209; JPX2-30454 19900209; JPX2-49312 19900302
- 主分类号: H01L27/11
- IPC分类号: H01L27/11 ; H01L21/8244
摘要:
A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.
公开/授权文献
- US5045861A Navigation and tracking system 公开/授权日:1991-09-03
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