公开(公告)号：US20070234168A1

公开(公告)日：2007-10-04

申请号：US11704370

申请日：2007-02-09

申请人： Nobuyuki Moriwaki ,  Takehiro Hirai

发明人： Nobuyuki Moriwaki ,  Takehiro Hirai

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31722

摘要： A semiconductor integrated circuit device includes: a plurality of devices under test formed on a substrate; a selection circuit formed on the substrate which selects two of the plurality of devices under test; a magnitude comparison circuit formed on the substrate which measures an electrical characteristic of the two selected devices under test and makes a magnitude comparison between values of the measured electrical characteristic; an address memory circuit formed on the substrate which stores addresses of the two devices under test between which the magnitude comparison has been made; and a control circuit formed on the substrate and connected to the selection circuit, the magnitude comparison circuit, and the address memory circuit.

摘要翻译： 半导体集成电路器件包括：在基片上形成的多个被测器件; 选择电路，形成在所述基板上，所述选择电路选择所述多个被测器件中的两个; 形成在所述基板上的幅度比较电路，其测量所述被测器件的电特性，并且对所测量的电特性的值进行幅度比较; 形成在基板上的地址存储电路，其存储已经进行了大小比较的被测器件的地址; 以及形成在基板上并连接到选择电路，幅度比较电路和地址存储电路的控制电路。

公开(公告)号：US06927594B2

公开(公告)日：2005-08-09

申请号：US10869872

申请日：2004-06-18

申请人： Sugao Fujinaga ,  Nobuyuki Moriwaki

发明人： Sugao Fujinaga ,  Nobuyuki Moriwaki

IPC分类号： H01L21/66 ,  G11C29/02 ,  H01L21/3205 ,  H01L23/52 ,  G01R31/26

CPC分类号： G11C29/025 ,  G11C29/02 ,  H01L2924/0002 ,  H01L2924/00

摘要： An evaluation device for evaluating a semiconductor device, used for evaluating electric characteristics of an electrical connection member provided in a vertical direction to a substrate surface, includes a unit circuit having a switching transistor in which a gate thereof connected to a signal line and one of a source and a drain thereof is connected to a first interconnect, and a first resistance element in which one terminal is connected to the other one of the source and the drain of the switching transistor and the other terminal is connected to a second interconnect. The first resistance element constituting each unit circuit includes at least one electrical connection member.

摘要翻译： 用于评估用于评估在垂直方向上设置在基板表面上的电连接部件的电特性的半导体装置的评估装置包括具有开关晶体管的单元电路，其中连接到信号线的栅极和 其源极和漏极连接到第一互连，并且第一电阻元件，其中一个端子连接到开关晶体管的源极和漏极中的另一个，而另一个端子连接到第二互连。 构成每个单元电路的第一电阻元件包括至少一个电连接构件。

公开(公告)号：US5834851A

公开(公告)日：1998-11-10

申请号：US460641

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5467302A

公开(公告)日：1995-11-14

申请号：US354476

申请日：1994-12-12

申请人： Hiroshige Hirano ,  Tatsumi Sumi ,  Nobuyuki Moriwaki ,  George Nakane

发明人： Hiroshige Hirano ,  Tatsumi Sumi ,  Nobuyuki Moriwaki ,  George Nakane

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first ferrodielectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second ferrodielectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the ferrodielectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.

摘要翻译： 位线BL0和/ BL0连接到读出放大器SA0，第一MOS晶体管的栅极连接到第一字线WL0，第一电介质电容器Cs1的第一电极到第一Qn的源极，第一 Qn至BL0，Cs1的第二电极到第一平板电极CP0，第二MOS晶体管Qn的栅极到第二字线DWL0，第二电介质电容器Cd2的第一电极到第二Qn的源极，漏极 的第二Qn至/ BL0的第二电极，以及Cd1的第二电极到第二平板电极DCP0，并且在关闭第二Qn之后，DCP0的逻辑电压反转。 因此，在采用强电介质元件的半导体存储器件中，虚拟存储电容器被可靠地初始化，并且能够在没有功耗集中的情况下实现高速读取。

公开(公告)号：US5396100A

公开(公告)日：1995-03-07

申请号：US861366

申请日：1992-03-31

申请人： Kohji Yamasaki ,  Nobuyuki Moriwaki ,  Shuji Ikeda ,  Hideaki Nakamura ,  Shigeru Honjo

发明人： Kohji Yamasaki ,  Nobuyuki Moriwaki ,  Shuji Ikeda ,  Hideaki Nakamura ,  Shigeru Honjo

IPC分类号： H01L27/02 ,  H01L27/11 ,  H01L29/76 ,  H01L23/552 ,  H01L27/10

CPC分类号： H01L27/1108 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S257/903

摘要： Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

摘要翻译： 这里公开了一种半导体集成电路器件，其具有由矩阵形状规则地排列的存储单元形成的存储器阵列或存储器垫。 在存储器单元的图案化中断或中断的器件的区域中的存储器阵列或存储单元的端部或内部，形成用于调节具有图案的存储单元的元件隔离绝缘膜的形状 使得与存储单元的图形不间断规则形式的装置区域中用于调节存储单元的元件隔离绝缘膜的形状基本相同。 在与存储区域相关联的规则图案的芯片正面上的位置中断的情况下，形成具有与布置在位置的端部的栅电极的形状基本相同的形状的虚设图案，其中规则图案 被中断。

公开(公告)号：US4797717A

公开(公告)日：1989-01-10

申请号：US039291

申请日：1987-04-17

申请人： Koichiro Ishibashi ,  Osamu Minato ,  Toshiaki Masuhara ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Shoji Hanamura ,  Nobuyuki Moriwaki ,  Shigeru Honjyo ,  Kiyotsugu Ueda

发明人： Koichiro Ishibashi ,  Osamu Minato ,  Toshiaki Masuhara ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Shoji Hanamura ,  Nobuyuki Moriwaki ,  Shigeru Honjyo ,  Kiyotsugu Ueda

IPC分类号： G11C11/403 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/45 ,  H01L29/78 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L29/456 ,  H01L27/1112 ,  Y10S257/904

摘要： Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

摘要翻译： SRAM中的每个存储单元包括两个驱动器MOS晶体管，两个传输门MOS晶体管和两个负载电阻。 MOS晶体管的栅极电极层由设置在半导体衬底的表面上的第一级导电层形成。 每个存储单元中的两个驱动器MOS晶体管的源极区域共同连接，并且通过第二级导电层进一步连接到地电位点。 每个存储单元中的两个负载电阻由第三级高电阻材料层形成。 第二级导电层由低电阻材料层形成。 因此，两个驱动器MOS晶体管的源极的电阻降低。

公开(公告)号：US4747082A

公开(公告)日：1988-05-24

申请号：US76174

申请日：1987-07-21

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

IPC分类号： G11C11/406 ,  G11C8/00

CPC分类号： G11C11/406

摘要： A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

摘要翻译： 半导体存储器设置有自动刷新装置，包括定时器，刷新计数器和刷新缓冲器，每个形成在安装有异步存储器的半导体芯片上，用于基于生成的基本时钟信号自动执行周期性刷新操作 响应于对刷新计数器的输出的逻辑改变的检测。 自动刷新计数器包括优先于周期性刷新操作执行基于与周期性刷新操作异步的常规地址信号的读操作和写操作之一的装置。

公开(公告)号：US6038160A

公开(公告)日：2000-03-14

申请号：US981441

申请日：1998-05-28

申请人： Joji Nakane ,  Nobuyuki Moriwaki

发明人： Joji Nakane ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A semiconductor memory device of nonvolatile ferroelectric capable of stable operation without loss of logic voltage "L" data of the memory cell in rewriting operation. To achieve, for example, as shown in FIG. 1, diodes 1, 2 are connected to cell plate lines 39, 40. Therefore, in rewriting operation, if there is a parasitic resistance 3 in the cell plate line 39, it is possible to prevent occurrence of transient phenomenon of temporary transition of the cell plate line 39 to an excessive negative voltage (for example, lower than -1V) which may cause loss of data.

摘要翻译： PCT No.PCT / JP97 / 01267 Sec。 371日期：1998年5月28日 102（e）日期1998年5月28日PCT 1997年11月4日PCT PCT。 公开号WO97 / 40500 PCT 日期：1997年10月30日一种不挥发性铁电体的半导体存储器件，能够在重写操作中不损失存储单元的逻辑电压“L”数据而稳定地操作。 为了实现，例如，如图1所示。 如图1所示，二极管1,2连接到单元板线39,40。因此，在重写操作中，如果在单元板线39中存在寄生电阻3，则可以防止发生临时转换的瞬态现象 电池板线39到可能导致数据丢失的过大的负电压（例如低于-1V）。

公开(公告)号：US5828615A

公开(公告)日：1998-10-27

申请号：US785838

申请日：1997-01-08

申请人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

发明人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/22 ,  G11C11/401 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22

摘要： A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

摘要翻译： 参考电位发生器由两条信号线21和22组成; 电荷供给装置，用于向信号线21和22提供电荷; 连接充电提供电路23和两条信号线21和22的第一连接电路24a和24b，以向两条信号线提供电荷; 以及通过第二控制信号将两个信号线21和22连接在一起的第二连接电路25，并且在由所提供的电荷确定的两个信号线的电位和信号线的每个负载电容被平均后，两个信号线被断开。 结合上述参考电位发生器产生精确参考电位的本发明的半导体存储器件能够放大并输出参考电位与位线中的数据读出电位之间的电位差，由此“1” 或读出数据的“0”。

公开(公告)号：US5767554A

公开(公告)日：1998-06-16

申请号：US460639

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。