A semiconductor memory device comprises an array of electrically rewritable memory cells which are arranged in a matrix, erasing section for applying an erasing voltage to the memory cells to effect erasing, and writing section for applying a writing voltage to the memory cells to effect writing, wherein in the erasing section and writing section, either MOS transistors to which a voltage higher than the erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than the erasing voltage and writing voltage contain MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V.