公开(公告)号：US06282117B1

公开(公告)日：2001-08-28

申请号：US09532329

申请日：2000-03-21

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When, the number of multilevel data to be output to one bit line BL is 2m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is “m”. Specifically, when the number is determined such that 22=4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

摘要翻译： 提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。 位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。 当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。 具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。 结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

公开(公告)号：US06545909B2

公开(公告)日：2003-04-08

申请号：US10094215

申请日：2002-03-11

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to sense read data. Bit lines connect the bit line controllers and the memory cells. The bit lines supply write data from the latch circuits to the memory cells during data write mode and supply read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.

摘要翻译： 存储单元阵列，其中存储单元可存储多级数据以矩阵形式排列。 位线控制器具有被配置为锁存写入数据和被配置为感测读取数据的感测电路的锁存电路。 位线连接位线控制器和存储单元。 在数据写入模式期间，位线将写入数据从锁存电路提供给存储器单元，并且在数据读取模式期间将读取数据从存储器单元提供给读出电路。 多级数据的数量为4，感测电路的数量为2，多级数据的数量为8，感测电路的数量为3。

公开(公告)号：US6044013A

公开(公告)日：2000-03-28

申请号：US314446

申请日：1999-05-19

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

摘要翻译： 提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。 位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。 当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。 具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。 结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

公开(公告)号：US5828621A

公开(公告)日：1998-10-27

申请号：US941370

申请日：1997-09-30

申请人： Toru Tanzawa ,  Tomoharu Tanaka ,  Ken Takeuchi

发明人： Toru Tanzawa ,  Tomoharu Tanaka ,  Ken Takeuchi

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/028 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/83 ,  G11C16/04 ,  G11C2029/5004

摘要： A semiconductor memory device comprises an array of electrically rewritable memory cells which are arranged in a matrix, erasing section for applying an erasing voltage to the memory cells to effect erasing, and writing section for applying a writing voltage to the memory cells to effect writing, wherein in the erasing section and writing section, either MOS transistors to which a voltage higher than the erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than the erasing voltage and writing voltage contain MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V.

公开(公告)号：US5708606A

公开(公告)日：1998-01-13

申请号：US773893

申请日：1997-01-17

申请人： Toru Tanzawa ,  Tomoharu Tanaka ,  Ken Takeuchi

发明人： Toru Tanzawa ,  Tomoharu Tanaka ,  Ken Takeuchi

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  G11C29/50 ,  G11C16/00

CPC分类号： G11C29/028 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/83 ,  G11C16/04 ,  G11C2029/5004

摘要： A semiconductor memory device comprises an array of electrically rewritable memory cells which are arranged in a matrix, erasing section for applying an erasing voltage to the memory cells to effect erasing, and writing section for applying a writing voltage to the memory cells to effect writing, wherein in the erasing section and writing section, either MOS transistors to which a voltage higher than the erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than the erasing voltage and writing voltage contain MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V.

公开(公告)号：US5909398A

公开(公告)日：1999-06-01

申请号：US168379

申请日：1998-10-08

申请人： Toru Tanzawa ,  Tomoharu Tanaka ,  Ken Takeuchi

发明人： Toru Tanzawa ,  Tomoharu Tanaka ,  Ken Takeuchi

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  G11C29/50 ,  G11C16/00

CPC分类号： G11C29/028 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/83 ,  G11C16/04 ,  G11C2029/5004

摘要： A semiconductor memory device comprises an array of electrically rewritable memory cells which are arranged in a matrix, erasing section for applying an erasing voltage to the memory cells to effect erasing, and writing section for applying a writing voltage to the memory cells to effect writing, wherein in the erasing section and writing section, either MOS transistors to which a voltage higher than the erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than the erasing voltage and writing voltage contain MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V.

摘要翻译： 一种半导体存储器件，包括排列成矩阵的电可重写存储器单元阵列，用于将擦除电压施加到存储单元以进行擦除的擦除部分，以及用于向存储器单元施加写入电压以写入的写入部分， 其中在擦除部分和写入部分中，施加高于擦除电压和写入电压的电压的MOS晶体管或传输高于擦除电压和写入电压的电压的MOS晶体管包含处于弱反转的MOS晶体管 状态或反向状态，其基极偏置电压，栅极电压和源极电压为0 V.

公开(公告)号：US5969985A

公开(公告)日：1999-10-19

申请号：US816830

申请日：1997-03-18

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

公开(公告)号：US06363010B1

公开(公告)日：2002-03-26

申请号：US09899290

申请日：2001-07-06

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C1604

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is “m”. Specifically, when the number is determined such that 22=4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

公开(公告)号：US5905691A

公开(公告)日：1999-05-18

申请号：US83949

申请日：1998-05-26

申请人： Toru Tanzawa ,  Ken Takeuchi ,  Tomoharu Tanaka

发明人： Toru Tanzawa ,  Ken Takeuchi ,  Tomoharu Tanaka

IPC分类号： G01R31/28 ,  G11C16/04 ,  G11C16/06 ,  G11C29/14 ,  G11C29/34 ,  G11C29/46 ,  G11C8/00

CPC分类号： G11C29/14 ,  G11C29/46

摘要： A command register recognizes a batch-write test mode and outputs to a clock generating circuit signals indicating the recognition of the mode. In the batch-write test mode, the clock generating circuit generates a clock signal having a longer cycle than a clock signal generated in a normal operation mode. The clock signal is supplied to a row decoder (word line potential control circuit) to control the operation of the row decoder, so that the row decoder supplies a sufficient write potential to all word lines.

摘要翻译： 命令寄存器识别批量写入测试模式并输出到时钟产生电路，指示模式识别的信号。 在批量写入测试模式中，时钟产生电路产生具有比在正常操作模式中产生的时钟信号更长的周期的时钟信号。 时钟信号被提供给行解码器（字线电位控制电路）以控制行解码器的操作，使得行解码器向所有字线提供足够的写入电位。

公开(公告)号：US5864504A

公开(公告)日：1999-01-26

申请号：US747761

申请日：1996-11-13

申请人： Toru Tanzawa ,  Tomoharu Tanaka ,  Ken Takeuchi

发明人： Toru Tanzawa ,  Tomoharu Tanaka ,  Ken Takeuchi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C7/14 ,  G11C11/56 ,  G11C16/06 ,  G11C16/28 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： G11C7/04 ,  G11C11/5642 ,  G11C16/28 ,  G11C5/147 ,  G11C7/14

摘要： An electrically erasable programmable read only memory (EEPROM) capable of reducing the margin of threshold voltage is disclosed which contributes to the achievement of low-voltage driving and/or multiple-value data storage architectures. The EEPROM includes an array of memory cells that are changeable in threshold voltage for data storage of different logic levels, wherein data may be read out of any specified one of the memory cells. A read voltage applied to the memory cell is designed to have a temperature dependence substantially identical to that of the memory-cell threshold voltage. A write-verify voltage may also be designed to have the same temperature dependence as that of the memory cell. Thus, the inter-threshold margin and the read margins of the memory cell can be reduced.

摘要翻译： 公开了能够降低阈值电压裕度的电可擦除可编程只读存储器（EEPROM），其有助于实现低电压驱动和/或多值数据存储架构。 EEPROM包括可以用于不同逻辑电平的数据存储的阈值电压可变的存储器单元阵列，其中可以从任何指定的一个存储器单元中读出数据。 施加到存储单元的读取电压被设计为具有与存储单元阈值电压基本相同的温度依赖性。 写验证电压也可以被设计为具有与存储器单元相同的温度依赖性。 因此，可以减小存储单元的阈值间距和读取余量。