发明授权
US5712532A Scalable CRT display device and phase synchronous circuit for use in
display device
失效
可扩展的CRT显示设备和用于显示设备的相位同步电路
- 专利标题: Scalable CRT display device and phase synchronous circuit for use in display device
- 专利标题(中): 可扩展的CRT显示设备和用于显示设备的相位同步电路
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申请号: US306711申请日: 1994-09-15
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公开(公告)号: US5712532A公开(公告)日: 1998-01-27
- 发明人: Masanori Ogino , Yoshiyuki Imoto , Kunio Umehara , Jiro Kawasaki , Kiyoshi Yamamoto , Miyuki Ikeda , Kazutaka Naka
- 申请人: Masanori Ogino , Yoshiyuki Imoto , Kunio Umehara , Jiro Kawasaki , Kiyoshi Yamamoto , Miyuki Ikeda , Kazutaka Naka
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX6-065859 19940404; JPX6-094135 19940506
- 主分类号: G09G1/04
- IPC分类号: G09G1/04 ; H04N3/233 ; H04N3/26 ; H04N3/27 ; H04N9/64 ; H01V29/98
摘要:
A CRT display device capable of displaying a signal from the existing image signal source, in which a vertical frequency is approximately fixed and a horizontal frequency is widely distributed beyond a ratio of 3:1, on one image screen. The CRT display device includes a scan converter unit and a display unit. The scan converter unit includes an output horizontal frequency unifying circuit, a horizontal blanking period ratio converting circuit, a vertical frequency converting unit and a vertical blanking period ratio converting circuit. The display unit includes a vertical deflection circuit and a circuit for correcting a vertical S-shaped distortion. In a phase synchronous circuit, a lock-out detector is connected to an output of a three state output digital phase detector, and on the basis of an output thereof, a switch is subjected to the "ON"/"OFF" control. For a period of time when an output of the lock-out detector indicates a lock-out state, a loop gain of the PLL is increased and the pull-in time is shortened. For the remaining periods of time, i.e., in the steady state, the loop gain is decreased and the noise resistance characteristics are improved.
公开/授权文献
- US4459765A Heel-counter stabilizer 公开/授权日:1984-07-17
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