A microprocessor has N processing units, a detector for detecting a branch instruction (k-th instruction) which comes first in the instruction sequence of N instructions, function logic for effecting control such that the first to the k-th instructions are executed with the (N-k+1)-th through the N-th processing units. However, when parallel processing is possible, the function logic operates such that the first through the N-th instructions are executed in sequential order by the first through the N-th processing units. On the other hand, wherein a branch instruction (k-th instruction) is included in the N sequential instructions, the function logic operates such that the first through the k-th instructions are parallelly executed by the (N-p+1)-th through the N-th processing units.