发明授权
US5729721A Timebase synchronization in separate integrated circuits or separate modules 失效
在单独的集成电路或单独模块中的时基同步

Timebase synchronization in separate integrated circuits or separate
modules
摘要:
Timebase channels in different I/O control modules (IOCMs 281-284 in FIG. 16) or on different integrated circuits (300-302 in FIG. 17 ) may provide synchronized, coherent timebase values to different blocks of work and other channels (e.g. 86 in FIG. 2) that are coupled to different timer buses (e.g. 71 in FIG. 2). In one embodiment, referring to FIGS. 1-19, two or more timebase channels, e.g. master timebase channel (285) and slave timebase channel (288), can be synchronized and kept in synchronization using just two signals, namely a clock signal (328) and a synchronization signal (329). The master timebase channel (285) generates or receives a master dock signal (328) which is coupled to one or more slave timebase channels (288) to ensure that the master and slave timebase channels (285, 288) increment or decrement at the same time and rate.
信息查询
0/0