A link system controller is interposed between a PCI bus and the CPU data bus and memory data bus of a personal computer system to ensure that the transfer of data from the PCI bus to the CPU data bus occurs on different clock signals from the transfer of data from the PCI bus to the memory data bus. This is accomplished by an authorizing circuit, which alternately enables a CPU bus interface controller and a memory data bus controller in response to alternating clock signals. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise below an acceptable threshold; so that the operation of the IC system device is not impaired.