- 专利标题: Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address
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申请号: US438919申请日: 1995-05-10
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公开(公告)号: US5740114A公开(公告)日: 1998-04-14
- 发明人: Hiroshige Hirano , Hisakazu Kotani , Naomi Miyake
- 申请人: Hiroshige Hirano , Hisakazu Kotani , Naomi Miyake
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JPX Osaka
- 优先权: JPX4-064582 19920323; JPX4-168783 19920626
- 主分类号: G11C29/00
- IPC分类号: G11C29/00 ; G11C29/24 ; G11C7/00
摘要:
An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.
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