An interrupt control device of an embedded microcomputer including I/O devices and a processor core comprising: a program storage unit for storing interrupt processing programs, each corresponding to an interrupt level of an interrupt request signal, in sequential areas; a start address hold unit for holding start addresses, which can be updated, of the interrupt processing programs; a level hold unit for holding an interrupt level, which can be updated, of each interrupt signal inputted from the I/O devices; an interrupt reception unit for, when at least one of the interrupt signals is inputted, receiving an interrupt signal of a highest interrupt level out of the inputted interrupt signals and outputting an interrupt request signal of the same interrupt level; and a control unit for controlling a branch, when the interrupt request signal is outputted, by fetching one of the start addresses which corresponds to the interrupt level of the interrupt request signal from the start address hold unit and setting the start address in the program counter.